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Message-ID: <e2ba43d4-3991-e98e-6ec0-6ff3ad5d954b@samsung.com>
Date: Tue, 27 Oct 2020 13:28:55 +0100
From: Marek Szyprowski <m.szyprowski@...sung.com>
To: Rob Herring <robh+dt@...nel.org>
Cc: linux-samsung-soc <linux-samsung-soc@...r.kernel.org>,
PCI <linux-pci@...r.kernel.org>, devicetree@...r.kernel.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Jaehoon Chung <jh80.chung@...sung.com>,
Jingoo Han <jingoohan1@...il.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...com>
Subject: Re: [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to
support Exynos5433 PCIe PHY
Hi Rob,
On 26.10.2020 19:50, Rob Herring wrote:
> On Fri, Oct 23, 2020 at 2:58 AM Marek Szyprowski
> <m.szyprowski@...sung.com> wrote:
>> From: Jaehoon Chung <jh80.chung@...sung.com>
>>
>> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
>> dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
>> variant found in the Exynos5433 SoCs.
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@...sung.com>
>> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased
>> onto current kernel code, rewrote commit message]
>> Signed-off-by: Marek Szyprowski <m.szyprowski@...sung.com>
>> Acked-by: Krzysztof Kozlowski <krzk@...nel.org>
>> ---
>> drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
>> 1 file changed, 112 insertions(+), 192 deletions(-)
>>
>> diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
>> index 7e28b1aea0d1..d91de323dd0e 100644
>> --- a/drivers/phy/samsung/phy-exynos-pcie.c
>> +++ b/drivers/phy/samsung/phy-exynos-pcie.c
>> @@ -4,70 +4,41 @@
>> *
>> * Phy provider for PCIe controller on Exynos SoC series
>> *
>> - * Copyright (C) 2017 Samsung Electronics Co., Ltd.
>> + * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
>> * Jaehoon Chung <jh80.chung@...sung.com>
>> */
>>
>> -#include <linux/delay.h>
>> #include <linux/io.h>
>> -#include <linux/iopoll.h>
>> -#include <linux/init.h>
>> #include <linux/mfd/syscon.h>
>> -#include <linux/of.h>
>> -#include <linux/of_address.h>
>> #include <linux/of_platform.h>
>> #include <linux/platform_device.h>
>> #include <linux/phy/phy.h>
>> #include <linux/regmap.h>
>>
>> -/* PCIe Purple registers */
>> -#define PCIE_PHY_GLOBAL_RESET 0x000
>> -#define PCIE_PHY_COMMON_RESET 0x004
>> -#define PCIE_PHY_CMN_REG 0x008
>> -#define PCIE_PHY_MAC_RESET 0x00c
>> -#define PCIE_PHY_PLL_LOCKED 0x010
>> -#define PCIE_PHY_TRSVREG_RESET 0x020
>> -#define PCIE_PHY_TRSV_RESET 0x024
>> -
>> -/* PCIe PHY registers */
>> -#define PCIE_PHY_IMPEDANCE 0x004
>> -#define PCIE_PHY_PLL_DIV_0 0x008
>> -#define PCIE_PHY_PLL_BIAS 0x00c
>> -#define PCIE_PHY_DCC_FEEDBACK 0x014
>> -#define PCIE_PHY_PLL_DIV_1 0x05c
>> -#define PCIE_PHY_COMMON_POWER 0x064
>> -#define PCIE_PHY_COMMON_PD_CMN BIT(3)
>> -#define PCIE_PHY_TRSV0_EMP_LVL 0x084
>> -#define PCIE_PHY_TRSV0_DRV_LVL 0x088
>> -#define PCIE_PHY_TRSV0_RXCDR 0x0ac
>> -#define PCIE_PHY_TRSV0_POWER 0x0c4
>> -#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV0_LVCC 0x0dc
>> -#define PCIE_PHY_TRSV1_EMP_LVL 0x144
>> -#define PCIE_PHY_TRSV1_RXCDR 0x16c
>> -#define PCIE_PHY_TRSV1_POWER 0x184
>> -#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV1_LVCC 0x19c
>> -#define PCIE_PHY_TRSV2_EMP_LVL 0x204
>> -#define PCIE_PHY_TRSV2_RXCDR 0x22c
>> -#define PCIE_PHY_TRSV2_POWER 0x244
>> -#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV2_LVCC 0x25c
>> -#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
>> -#define PCIE_PHY_TRSV3_RXCDR 0x2ec
>> -#define PCIE_PHY_TRSV3_POWER 0x304
>> -#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV3_LVCC 0x31c
>> -
>> -struct exynos_pcie_phy_data {
>> - const struct phy_ops *ops;
>> -};
>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>> +
>> +/* Sysreg FSYS register offsets and bits for Exynos5433 */
>> +#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
>> +#define PCIE_MAC_RESET_MASK 0xFF
>> +#define PCIE_MAC_RESET BIT(4)
>> +#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
>> +#define PCIE_REFCLK_GATING_EN BIT(0)
>> +#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
>> +#define PCIE_PHY_RESET BIT(0)
>> +#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
>> +#define PCIE_GLOBAL_RESET BIT(0)
> Resets, why is this block not a reset provider?
Because most of those registers need to be configured together with the
rest of the PHY registers. IMHO there is no simple "do the reset" logic
there. There is also PHY reference clock configuration there. This phy
driver is already Exynos5433 specific and I see no point in extracting
separate reset driver from it. Other Exynos PHY drivers also access PMU
and SYSREG via the respective regmaps and don't use any kind of reset
drivers.
>> +#define PCIE_REFCLK BIT(1)
>> +#define PCIE_REFCLK_MASK 0x16
>> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
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