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Message-ID: <f7ac9562-6ba9-dc67-f2d7-cc5c1321f5d0@gmail.com>
Date: Tue, 27 Oct 2020 22:23:42 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Georgi Djakov <georgi.djakov@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Peter De Schrijver <pdeschrijver@...dia.com>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Mikko Perttunen <cyndis@...si.fi>,
Viresh Kumar <vireshk@...nel.org>,
Peter Geis <pgwipeout@...il.com>,
Nicolas Chauvet <kwizart@...il.com>,
linux-tegra@...r.kernel.org, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v6 22/52] ARM: tegra: Add interconnect properties to
Tegra30 device-tree
27.10.2020 12:15, Krzysztof Kozlowski пишет:
...>> @@ -748,15 +770,18 @@ mc: memory-controller@...0f000 {
>>
>> #iommu-cells = <1>;
>> #reset-cells = <1>;
>> + #interconnect-cells = <1>;
>> };
>>
>> - memory-controller@...0f400 {
>> + emc: memory-controller@...0f400 {
>> compatible = "nvidia,tegra30-emc";
>> reg = <0x7000f400 0x400>;
>> interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
>> clocks = <&tegra_car TEGRA30_CLK_EMC>;
>>
>> nvidia,memory-controller = <&mc>;
>> +
>
> No need for blank line.
It's needed to make MC and EMC nodes look consistent. See the MC node
above which has the blank line.
>
>> + #interconnect-cells = <0>;
>> };
>>
>> fuse@...0f800 {
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