linux-kernel - [PATCHv2 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20201027073001.41808-4-Zhiqiang.Hou@nxp.com>
Date:   Tue, 27 Oct 2020 15:29:57 +0800
From:   Zhiqiang Hou <Zhiqiang.Hou@....com>
To:     linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        lorenzo.pieralisi@....com, robh+dt@...nel.org, bhelgaas@...gle.com,
        shawnguo@...nel.org, leoyang.li@....com,
        gustavo.pimentel@...opsys.com
Cc:     minghuan.Lian@....com, mingkai.hu@....com, roy.zang@....com,
        Hou Zhiqiang <Zhiqiang.Hou@....com>
Subject: [PATCHv2 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian

From: Hou Zhiqiang <Zhiqiang.Hou@....com>

This property is to indicate the endianness when accessing the
PEX_LUT and PF register block, so if these registers are
implemented in big-endian, specify this property.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
Acked-by: Rob Herring <robh@...nel.org>
---
V2:
 - No change.

 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index daa99f7d4c3f..0033c898976e 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -39,6 +39,10 @@ Required properties:
   of the data transferred from/to the IP block. This can avoid the software
   cache flush/invalid actions, and improve the performance significantly.
 
+Optional properties:
+- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
+  this property.
+
 Example:
 
 	pcie@...0000 {
-- 
2.17.1