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Message-Id: <20201027073001.41808-7-Zhiqiang.Hou@nxp.com>
Date:   Tue, 27 Oct 2020 15:30:00 +0800
From:   Zhiqiang Hou <Zhiqiang.Hou@....com>
To:     linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        lorenzo.pieralisi@....com, robh+dt@...nel.org, bhelgaas@...gle.com,
        shawnguo@...nel.org, leoyang.li@....com,
        gustavo.pimentel@...opsys.com
Cc:     minghuan.Lian@....com, mingkai.hu@....com, roy.zang@....com,
        Hou Zhiqiang <Zhiqiang.Hou@....com>
Subject: [PATCHv2 6/7] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes

From: Hou Zhiqiang <Zhiqiang.Hou@....com>

The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
---
V2:
 - Correct the order of the subject prefixes.

 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index d33a64ae8b0f..23bf3796d98f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -822,6 +822,7 @@
 			interrupts = <0 118 0x4>, /* controller interrupt */
 				     <0 117 0x4>; /* PME interrupt */
 			interrupt-names = "intr", "pme";
+			fsl,pcie-scfg = <&scfg 0>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -849,6 +850,7 @@
 			interrupts = <0 128 0x4>,
 				     <0 127 0x4>;
 			interrupt-names = "intr", "pme";
+			fsl,pcie-scfg = <&scfg 1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -876,6 +878,7 @@
 			interrupts = <0 162 0x4>,
 				     <0 161 0x4>;
 			interrupt-names = "intr", "pme";
+			fsl,pcie-scfg = <&scfg 2>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-- 
2.17.1

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