linux-kernel - Re: [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read & write support

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Message-ID: <a6f65077-f435-4c8e-994e-38e2f5d437b1@microchip.com>
Date:   Wed, 28 Oct 2020 10:18:30 +0000
From:   <Tudor.Ambarus@...rochip.com>
To:     <masonccyang@...c.com.tw>, <broonie@...nel.org>,
        <miquel.raynal@...tlin.com>, <richard@....at>, <vigneshr@...com>,
        <boris.brezillon@...labora.com>, <matthias.bgg@...il.com>
CC:     <juliensu@...c.com.tw>, <linux-kernel@...r.kernel.org>,
        <linux-spi@...r.kernel.org>, <linux-mtd@...ts.infradead.org>,
        <p.yadav@...com>, <ycllin@...c.com.tw>
Subject: Re: [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2
 read & write support

Hi, Mason, YC Lin,

On 5/29/20 10:36 AM, Mason Yang wrote:
> Configuration register 2 is to set the device operation condition like
> STR or DTR mode at address offset 0 and DQS mode at address offset 0x200.
> 
> Each device has various address offset for it's specific operatoin
> setting.
> 
> Signed-off-by: Mason Yang <masonccyang@...c.com.tw>
> ---
>  drivers/mtd/spi-nor/core.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/mtd/spi-nor/core.h |  2 ++
>  2 files changed, 80 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 3799417..fed6236 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -269,6 +269,84 @@ int spi_nor_write_disable(struct spi_nor *nor)
>  }
>  
>  /**
> + * spi_nor_read_cr2() - Read the Configuration Register 2.
> + * @nor:	pointer to 'struct spi_nor'.
> + * @addr:	offset address to read.
> + * @cr2:	pointer to a DMA-able buffer where the value of the
> + *              Configuration Register 2  will be written.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +int spi_nor_read_cr2(struct spi_nor *nor, u32 addr, u8 *cr2)

spi_nor_read_volatile_reg() please

do we need to pass len as an argument?

s/cr2/buf

why do we need addr for register interactions?

> +{
> +	int ret;
> +	u8 cmd = nor->params->rd_reg_cmd;

you'll need to redefine to rd_vreg_cmd.

> +
> +	if (nor->spimem) {
> +		struct spi_mem_op op =
> +			SPI_MEM_OP(SPI_MEM_OP_CMD(cmd, 1),
> +				   SPI_MEM_OP_ADDR(4, addr, 1),

nor->addr_width?

> +				   SPI_MEM_OP_DUMMY(4, 1),

nor->read_dummy?

> +				   SPI_MEM_OP_DATA_IN(1, cr2, 1));

SPI_MEM_OP_DATA_IN(len, cr2, 0)?
> +
> +		spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
> +
> +		ret = spi_mem_exec_op(nor->spimem, &op);
> +	} else {
> +		if (spi_nor_protocol_is_dtr(nor->reg_proto))
> +			ret = -ENOTSUPP;
> +		else
> +			ret = nor->controller_ops->read_reg(nor, cmd, cr2, 1);
> +	}
> +
> +	if (ret)
> +		dev_dbg(nor->dev, "error %d reading CR2\n", ret);
> +
> +	return ret;
> +}
> +
> +/**
> + * spi_nor_write_cr2() - Write the Configuration Register 2.
> + * @nor:	pointer to 'struct spi_nor'.
> + * @addr:	offset address to write.
> + * @cr2:	pointer to a DMA-able buffer where the value of the
> + *              Configuratin Register 2 will be read.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +int spi_nor_write_cr2(struct spi_nor *nor, u32 addr, u8 *cr2)

spi_nor_write_volatile_reg() please

Cheers,
ta