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Date:   Wed, 28 Oct 2020 16:35:25 +0100
From:   Krzysztof Kozlowski <krzk@...nel.org>
To:     Rob Herring <robh@...nel.org>
Cc:     Dmitry Osipenko <digetx@...il.com>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Georgi Djakov <georgi.djakov@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Peter De Schrijver <pdeschrijver@...dia.com>,
        MyungJoo Ham <myungjoo.ham@...sung.com>,
        Kyungmin Park <kyungmin.park@...sung.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Mikko Perttunen <cyndis@...si.fi>,
        Viresh Kumar <vireshk@...nel.org>,
        Peter Geis <pgwipeout@...il.com>,
        Nicolas Chauvet <kwizart@...il.com>,
        linux-tegra@...r.kernel.org, linux-pm@...r.kernel.org,
        linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH v6 04/52] dt-bindings: memory: tegra20: emc: Document
 nvidia,memory-controller property

On Wed, Oct 28, 2020 at 10:23:03AM -0500, Rob Herring wrote:
> On Tue, Oct 27, 2020 at 08:30:39PM +0100, Krzysztof Kozlowski wrote:
> > On Tue, Oct 27, 2020 at 10:17:19PM +0300, Dmitry Osipenko wrote:
> > > 27.10.2020 11:54, Krzysztof Kozlowski пишет:
> > > > On Mon, Oct 26, 2020 at 01:16:47AM +0300, Dmitry Osipenko wrote:
> > > >> Tegra20 External Memory Controller talks to DRAM chips and it needs to be
> > > >> reprogrammed when memory frequency changes. Tegra Memory Controller sits
> > > >> behind EMC and these controllers are tightly coupled. This patch adds the
> > > >> new phandle property which allows to properly express connection of EMC
> > > >> and MC hardware in a device-tree, it also put the Tegra20 EMC binding on
> > > >> par with Tegra30+ EMC bindings, which is handy to have.
> > > >>
> > > >> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> > > >> ---
> > > >>  .../bindings/memory-controllers/nvidia,tegra20-emc.txt          | 2 ++
> > > >>  1 file changed, 2 insertions(+)
> > > >>
> > > >> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
> > > >> index 567cffd37f3f..1b0d4417aad8 100644
> > > >> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
> > > >> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
> > > >> @@ -12,6 +12,7 @@ Properties:
> > > >>    irrespective of ram-code configuration.
> > > >>  - interrupts : Should contain EMC General interrupt.
> > > >>  - clocks : Should contain EMC clock.
> > > >> +- nvidia,memory-controller : Phandle of the Memory Controller node.
> > > > 
> > > > It looks like you adding a required property which is an ABI break.
> > > The T20 EMC driver is unused so far in upstream and it will become used
> > > only once this series is applied. Hence it's fine to change the ABI.
> > 
> > The ABI is not about upstream, but downstream. 
> 
> "If it's not upstream, it doesn't exist."
> 
> Though we do have to account for out of tree users where the DT is not 
> in tree, but upstream drivers are used. Downstream as in vendor kernels 
> typically has loads of other crap.

That's the case I am referring to. Maybe not in case of Tegra, but
multiple other designs are quite popular in industrial uses and their
DTSes were not upstreamed.

This is anyway different case, as Dmitry explained - nothing got broken
because not much was working before around this.

> 
> > There are no other
> > upstreams using this ABI. Unless you have in mind that existing T20 EMC
> > driver was a noop, doing absolutely nothing, therefore there is no
> > breakage of any other users?
> 
> ABI breaks are ultimately up to the platform maintainers to decide.

Cool! That reshapes significantly my existing point of view, especially
about discussions on Exynos bindings (long time ago). Thanks for
clarification.

Best regards,
Krzysztof

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