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Message-ID: <1603898561-5142-1-git-send-email-sjakhade@cadence.com>
Date: Wed, 28 Oct 2020 16:22:41 +0100
From: Swapnil Jakhade <sjakhade@...ence.com>
To: <vkoul@...nel.org>, <kishon@...com>, <robh+dt@...nel.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
CC: <mparab@...ence.com>, <sjakhade@...ence.com>,
<yamonkar@...ence.com>, <tomi.valkeinen@...com>, <jsarha@...com>,
<nsekhar@...com>
Subject: [PATCH] dt-bindings: phy: Add Cadence Sierra PHY bindings in YAML format
Add Cadence Sierra PHY bindings in YAML format.
Signed-off-by: Swapnil Jakhade <sjakhade@...ence.com>
---
.../bindings/phy/phy-cadence-sierra.txt | 70 --------
.../bindings/phy/phy-cadence-sierra.yaml | 152 ++++++++++++++++++
2 files changed, 152 insertions(+), 70 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
deleted file mode 100644
index 03f5939d3d19..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-Cadence Sierra PHY
------------------------
-
-Required properties:
-- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
- Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
-- resets: Must contain an entry for each in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include "sierra_reset" and "sierra_apb".
- "sierra_reset" must control the reset line to the PHY.
- "sierra_apb" must control the reset line to the APB PHY
- interface ("sierra_apb" is optional).
-- reg: register range for the PHY.
-- #address-cells: Must be 1
-- #size-cells: Must be 0
-
-Optional properties:
-- clocks: Must contain an entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must contain "cmn_refclk_dig_div" and
- "cmn_refclk1_dig_div" for configuring the frequency of
- the clock to the lanes. "phy_clk" is deprecated.
-- cdns,autoconf: A boolean property whose presence indicates that the
- PHY registers will be configured by hardware. If not
- present, all sub-node optional properties must be
- provided.
-
-Sub-nodes:
- Each group of PHY lanes with a single master lane should be represented as
- a sub-node. Note that the actual configuration of each lane is determined by
- hardware strapping, and must match the configuration specified here.
-
-Sub-node required properties:
-- #phy-cells: Generic PHY binding; must be 0.
-- reg: The master lane number. This is the lowest numbered lane
- in the lane group.
-- resets: Must contain one entry which controls the reset line for the
- master lane of the sub-node.
- See ../reset/reset.txt for details.
-
-Sub-node optional properties:
-- cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
- group is made up of consecutive lanes.
-- cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
- configuration of lanes.
-
-Example:
- pcie_phy4: pcie-phy@...40000 {
- compatible = "cdns,sierra-phy-t0";
- reg = <0x0 0xfd240000 0x0 0x40000>;
- resets = <&phyrst 0>, <&phyrst 1>;
- reset-names = "sierra_reset", "sierra_apb";
- clocks = <&phyclock>;
- clock-names = "phy_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- pcie0_phy0: pcie-phy@0 {
- reg = <0>;
- resets = <&phyrst 2>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- };
- pcie0_phy1: pcie-phy@2 {
- reg = <2>;
- resets = <&phyrst 4>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- };
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
new file mode 100644
index 000000000000..d210843863df
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence Sierra PHY binding
+
+description:
+ This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
+ multiprotocol combinations including protocols such as PCIe, USB etc.
+
+maintainers:
+ - Swapnil Jakhade <sjakhade@...ence.com>
+ - Yuti Amonkar <yamonkar@...ence.com>
+
+properties:
+ compatible:
+ enum:
+ - cdns,sierra-phy-t0
+ - ti,sierra-phy-t0
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ resets:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: Sierra PHY reset.
+ - description: Sierra APB reset. This is optional.
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: sierra_reset
+ - const: sierra_apb
+
+ reg:
+ maxItems: 1
+ description:
+ Offset of the Sierra PHY configuration registers.
+
+ reg-names:
+ const: serdes
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: cmn_refclk_dig_div
+ - const: cmn_refclk1_dig_div
+
+ cdns,autoconf:
+ type: boolean
+ description:
+ A boolean property whose presence indicates that the PHY registers will be
+ configured by hardware. If not present, all sub-node optional properties
+ must be provided.
+
+patternProperties:
+ '^phy@[0-9a-f]$':
+ type: object
+ description:
+ Each group of PHY lanes with a single master lane should be represented as
+ a sub-node. Note that the actual configuration of each lane is determined
+ by hardware strapping, and must match the configuration specified here.
+ properties:
+ reg:
+ description:
+ The master lane number. This is the lowest numbered lane in the lane group.
+ minimum: 0
+ maximum: 15
+
+ resets:
+ minItems: 1
+ maxItems: 4
+ description:
+ Contains list of resets, one per lane, to get all the link lanes out of reset.
+
+ "#phy-cells":
+ const: 0
+
+ cdns,phy-type:
+ description:
+ Specifies the type of PHY for which the group of PHY lanes is used.
+ Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [2, 4]
+
+ cdns,num-lanes:
+ description:
+ Number of lanes in this group. The group is made up of consecutive lanes.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 16
+
+ required:
+ - reg
+ - resets
+ - "#phy-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sierra-phy@...40000 {
+ compatible = "cdns,sierra-phy-t0";
+ reg = <0x0 0xfd240000 0x0 0x40000>;
+ resets = <&phyrst 0>, <&phyrst 1>;
+ reset-names = "sierra_reset", "sierra_apb";
+ clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pcie0_phy0: phy@0 {
+ reg = <0>;
+ resets = <&phyrst 2>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ };
+ pcie0_phy1: phy@2 {
+ reg = <2>;
+ resets = <&phyrst 4>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ };
+ };
+ };
--
2.26.1
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