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Message-ID: <20201029051839.11245-3-vidyas@nvidia.com>
Date: Thu, 29 Oct 2020 10:48:37 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: <lorenzo.pieralisi@....com>, <robh+dt@...nel.org>,
<bhelgaas@...gle.com>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>, <amanharitsh123@...il.com>,
<dinghao.liu@....edu.cn>, <kw@...ux.com>
CC: <linux-pci@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <kthota@...dia.com>,
<mmaddireddy@...dia.com>, <vidyas@...dia.com>, <sagar.tv@...il.com>
Subject: [PATCH V2 2/4] PCI: tegra: Map configuration space as nGnRnE
As specified in the comment for pci_remap_cfgspace() define in
arch/arm64/include/asm/io.h file, PCIe configuration space should be
mapped as nGnRnE. Hence changing to dev_pci_remap_cfgspace() from
devm_ioremap_resource() for mapping DBI space as that is nothing but
the root port's own configuration space.
Signed-off-by: Vidya Sagar <vidyas@...dia.com>
---
V2:
* Changed 'Strongly Ordered' to 'nGnRnE'
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index b172b1d49713..7a0c64436861 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2108,7 +2108,9 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
}
pcie->dbi_res = dbi_res;
- pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
+ pci->dbi_base = devm_pci_remap_cfgspace(dev,
+ dbi_res->start,
+ resource_size(dbi_res));
if (IS_ERR(pci->dbi_base))
return PTR_ERR(pci->dbi_base);
--
2.17.1
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