linux-kernel - [tip: perf/core] perf/x86/msr: Add Rocket Lake CPU support

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Message-ID: <160396869901.397.12647985959685130395.tip-bot2@tip-bot2>
Date:   Thu, 29 Oct 2020 10:51:39 -0000
From:   "tip-bot2 for Kan Liang" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Kan Liang <kan.liang@...ux.intel.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        x86 <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: [tip: perf/core] perf/x86/msr: Add Rocket Lake CPU support

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     907a196fbc70a48338ee8512da32f70fd33c97eb
Gitweb:        https://git.kernel.org/tip/907a196fbc70a48338ee8512da32f70fd33c97eb
Author:        Kan Liang <kan.liang@...ux.intel.com>
AuthorDate:    Mon, 19 Oct 2020 08:35:27 -07:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Thu, 29 Oct 2020 11:00:40 +01:00

perf/x86/msr: Add Rocket Lake CPU support

Like Ice Lake and Tiger Lake, PPERF and SMI_COUNT MSRs are also
supported by Rocket Lake.

Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://lkml.kernel.org/r/20201019153528.13850-3-kan.liang@linux.intel.com
---
 arch/x86/events/msr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 4be8f9c..680404c 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -99,6 +99,7 @@ static bool test_intel(int idx, void *data)
 	case INTEL_FAM6_ICELAKE_D:
 	case INTEL_FAM6_TIGERLAKE_L:
 	case INTEL_FAM6_TIGERLAKE:
+	case INTEL_FAM6_ROCKETLAKE:
 		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
 			return true;
 		break;