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Message-ID: <ec52cedf-3a99-5ca1-ffbb-d8f8c4f62395@intel.com>
Date: Fri, 30 Oct 2020 15:49:22 -0700
From: Dave Jiang <dave.jiang@...el.com>
To: Jason Gunthorpe <jgg@...dia.com>
Cc: Bjorn Helgaas <helgaas@...nel.org>, vkoul@...nel.org,
megha.dey@...el.com, maz@...nel.org, bhelgaas@...gle.com,
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baolu.lu@...el.com, kevin.tian@...el.com, sanjay.k.kumar@...el.com,
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Subject: Re: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection
On 10/30/2020 3:45 PM, Jason Gunthorpe wrote:
> On Fri, Oct 30, 2020 at 02:20:03PM -0700, Dave Jiang wrote:
>> So the intel-iommu driver checks for the SIOV cap. And the idxd driver
>> checks for SIOV and IMS cap. There will be other upcoming drivers that will
>> check for such cap too. It is Intel vendor specific right now, but SIOV is
>> public and other vendors may implement to the spec. Is there a good place to
>> put the common capability check for that?
>
> I'm still really unhappy with these SIOV caps. It was explained this
> is just a hack to make up for pci_ims_array_create_msi_irq_domain()
> succeeding in VM cases when it doesn't actually work.
>
> Someday this is likely to get fixed, so tying platform behavior to PCI
> caps is completely wrong.
>
> This needs to be solved in the platform code,
> pci_ims_array_create_msi_irq_domain() should not succeed in these
> cases.
That sounds reasonable. Are you asking that the IMS cap check should gate the
success/failure of pci_ims_array_create_msi_irq_domain() rather than the driver?
>
> Jason
>
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