lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20201031182137.1879521-3-contact@paulk.fr>
Date:   Sat, 31 Oct 2020 19:21:30 +0100
From:   Paul Kocialkowski <contact@...lk.fr>
To:     devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Cc:     Rob Herring <robh+dt@...nel.org>,
        Maxime Ripard <mripard@...nel.org>,
        Chen-Yu Tsai <wens@...e.org>,
        Matteo Scordino <matteo.scordino@...il.com>,
        Icenowy Zheng <icenowy@...c.io>,
        Paul Kocialkowski <contact@...lk.fr>
Subject: [PATCH 2/9] ARM: dts: sun8i-v3: Add UART1 PG pins description

UART1 is often exposed through the PG pins (usually for the debug
console) on the V3. They are not available on V3s.

Describe these pins in device-tree.

Signed-off-by: Paul Kocialkowski <contact@...lk.fr>
---
 arch/arm/boot/dts/sun8i-v3.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi
index ca4672ed2e02..edf48e0471ad 100644
--- a/arch/arm/boot/dts/sun8i-v3.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3.dtsi
@@ -24,4 +24,10 @@ external_mdio: mdio@2 {
 
 &pio {
 	compatible = "allwinner,sun8i-v3-pinctrl";
+
+	/omit-if-no-ref/
+	uart1_pg_pins: uart1-pg-pins {
+		pins = "PG6", "PG7";
+		function = "uart1";
+	};
 };
-- 
2.28.0

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ