lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20201102111245.GA15392@zn.tnic>
Date:   Mon, 2 Nov 2020 12:12:45 +0100
From:   Borislav Petkov <bp@...en8.de>
To:     "Luck, Tony" <tony.luck@...el.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Philippe Conde <conde.philippe@...net.be>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] x86/mce: Enable additional error logging on certain
 Intel CPUs

On Fri, Oct 30, 2020 at 12:08:07PM -0700, Luck, Tony wrote:
> On Fri, Oct 30, 2020 at 12:04:03PM -0700, Luck, Tony wrote:
> 
> Bah, didn't notice this conversation didn't include LKML.
> 
> > The Xeon versions of Sandy Bridge, Ivy Bridge and Haswell support an
> > optional additional error logging mode which is enabled by an MSR.
> > 
> > Previously this mode was enabled from the mcelog(8) tool via /dev/cpu,
> > but the kernel is now very picky about which MSRs may be written. So
> > move the enabling into the kernel.
> > 
> > Suggested-by: Boris Petkov <bp@...en8.de>
> > Signed-off-by: Tony Luck <tony.luck@...el.com>
> > ---
> > 
> > N.B. I don't have any of these old systems in my lab any more. So
> > this is untested :-(

I do:

# rdmsr 0x0000017f
2

Thx for doing this, queued.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ