linux-kernel - Re: [PATCH v18 2/4] iommu/arm-smmu: Add a way for implementations to influence SCTLR

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Message-ID: <20201103172813.GA5934@jcrouse1-lnx.qualcomm.com>
Date:   Tue, 3 Nov 2020 10:28:13 -0700
From:   Jordan Crouse <jcrouse@...eaurora.org>
To:     Robin Murphy <robin.murphy@....com>
Cc:     linux-arm-msm@...r.kernel.org, iommu@...ts.linux-foundation.org,
        Will Deacon <will@...nel.org>,
        Rob Clark <robdclark@...omium.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Joerg Roedel <joro@...tes.org>,
        Krishna Reddy <vdumpa@...dia.com>,
        Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
        Stephen Boyd <swboyd@...omium.org>,
        Thierry Reding <treding@...dia.com>,
        Vivek Gautam <vivek.gautam@...eaurora.org>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v18 2/4] iommu/arm-smmu: Add a way for implementations to
 influence SCTLR

On Mon, Nov 02, 2020 at 06:18:45PM +0000, Robin Murphy wrote:
> On 2020-11-02 17:14, Jordan Crouse wrote:
> >From: Rob Clark <robdclark@...omium.org>
> >
> >For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
> >pending translations are not terminated on iova fault.  Otherwise
> >a terminated CP read could hang the GPU by returning invalid
> >command-stream data.
> >
> >Signed-off-by: Rob Clark <robdclark@...omium.org>
> >Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> >Signed-off-by: Jordan Crouse <jcrouse@...eaurora.org>
> >---
> >
> >  drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++
> >  drivers/iommu/arm/arm-smmu/arm-smmu.c      | 3 +++
> >  drivers/iommu/arm/arm-smmu/arm-smmu.h      | 3 +++
> >  3 files changed, 12 insertions(+)
> >
> >diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> >index 1e942eed2dfc..0663d7d26908 100644
> >--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> >+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> >@@ -129,6 +129,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
> >  	    (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
> >  		pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
> >+	/*
> >+	 * On the GPU device we want to process subsequent transactions after a
> >+	 * fault to keep the GPU from hanging
> >+	 */
> >+	smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF;
> >+
> >  	/*
> >  	 * Initialize private interface with GPU:
> >  	 */
> >diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> >index dad7fa86fbd4..1f06ab219819 100644
> >--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> >+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> >@@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
> >  	if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
> >  		reg |= ARM_SMMU_SCTLR_E;
> >+	reg |= cfg->sctlr_set;
> >+	reg &= ~cfg->sctlr_clr;
> 
> Since we now have a write_s2cr hook, I'm inclined to think that the
> consistency of a write_sctlr hook that could similarly apply its own
> arbitrary tweaks would make sense for this. Does anyone have any strong
> opinions?

None from me. That would make an eventual stall-on-fault implementation easier
too.

Jordan

> Robin.
> 
> >+
> >  	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
> >  }
> >diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> >index 6c5ff9999eae..ddf2ca4c923d 100644
> >--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
> >+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
> >@@ -144,6 +144,7 @@ enum arm_smmu_cbar_type {
> >  #define ARM_SMMU_CB_SCTLR		0x0
> >  #define ARM_SMMU_SCTLR_S1_ASIDPNE	BIT(12)
> >  #define ARM_SMMU_SCTLR_CFCFG		BIT(7)
> >+#define ARM_SMMU_SCTLR_HUPCF		BIT(8)
> >  #define ARM_SMMU_SCTLR_CFIE		BIT(6)
> >  #define ARM_SMMU_SCTLR_CFRE		BIT(5)
> >  #define ARM_SMMU_SCTLR_E		BIT(4)
> >@@ -341,6 +342,8 @@ struct arm_smmu_cfg {
> >  		u16			asid;
> >  		u16			vmid;
> >  	};
> >+	u32				sctlr_set;    /* extra bits to set in SCTLR */
> >+	u32				sctlr_clr;    /* bits to mask in SCTLR */
> >  	enum arm_smmu_cbar_type		cbar;
> >  	enum arm_smmu_context_fmt	fmt;
> >  };
> >

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