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Message-ID: <fc07251a-5339-781b-f12a-abfda5d5d2a2@codethink.co.uk>
Date: Tue, 3 Nov 2020 15:19:06 +0000
From: Ben Dooks <ben.dooks@...ethink.co.uk>
To: Atish Patra <atishp@...shpatra.org>
Cc: devicetree@...r.kernel.org, Albert Ou <aou@...s.berkeley.edu>,
Cyril.Jean@...rochip.com,
Daire McNamara <daire.mcnamara@...rochip.com>,
Anup Patel <anup.patel@....com>,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
Atish Patra <atish.patra@....com>,
Rob Herring <robh+dt@...nel.org>,
Alistair Francis <alistair.francis@....com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Padmarao Begari <padmarao.begari@...rochip.com>
Subject: Re: [RFC PATCH 2/3] RISC-V: Initial DTS for Microchip ICICLE board
On 03/11/2020 15:07, Atish Patra wrote:
>>> We could just modify the reg size but to allow more memory. I tried
>>> that for Linux but it didn't boot.
>>> Probably, DDR init code in HSS only initialized 1GB of memory.
>> Yes, it is only looking at the low window which is 1GiB max.
>> If it used the upper window it would get the 16GiB.
>>
>> I don't know how no-one noticed this issue before shipping a board
>> out with this. I have updated the firmware on my second board but
>> this only seems to currently fix a reboot issue with the eMMC.
>>
> We can't update the DT for Linux until there is a public release of
> the updated firmware
> with 2GB enabled.
Yeah, it is really annoying the boards turned up with a number of
issues including the half memory.
I assume there will be a new release of HSS and U-boot which at
worse can insert new memory nodes into the device tree.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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