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Message-Id: <20201104234427.26477-14-digetx@gmail.com>
Date: Thu, 5 Nov 2020 02:44:10 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Alan Stern <stern@...land.harvard.edu>,
Peter Chen <Peter.Chen@....com>,
Mark Brown <broonie@...nel.org>,
Liam Girdwood <lgirdwood@...il.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Lee Jones <lee.jones@...aro.org>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>,
Ulf Hansson <ulf.hansson@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Marek Szyprowski <m.szyprowski@...sung.com>,
Peter Geis <pgwipeout@...il.com>,
Nicolas Chauvet <kwizart@...il.com>
Cc: linux-samsung-soc@...r.kernel.org, devel@...verdev.osuosl.org,
linux-usb@...r.kernel.org, linux-pwm@...r.kernel.org,
linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-media@...r.kernel.org, linux-tegra@...r.kernel.org
Subject: [PATCH v1 13/30] drm/tegra: gr2d: Support OPP and SoC core voltage scaling
Add OPP and SoC core voltage scaling support to the GR2D driver.
This is required for enabling system-wide DVFS on Tegra SoCs.
Tested-by: Peter Geis <pgwipeout@...il.com>
Tested-by: Nicolas Chauvet <kwizart@...il.com>
Signed-off-by: Dmitry Osipenko <digetx@...il.com>
---
drivers/gpu/drm/tegra/gr2d.c | 136 +++++++++++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c
index f30aa86e4c9f..6d8f9419d908 100644
--- a/drivers/gpu/drm/tegra/gr2d.c
+++ b/drivers/gpu/drm/tegra/gr2d.c
@@ -7,6 +7,9 @@
#include <linux/iommu.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/pm_opp.h>
+
+#include <soc/tegra/fuse.h>
#include "drm.h"
#include "gem.h"
@@ -185,6 +188,135 @@ static const u32 gr2d_addr_regs[] = {
GR2D_VA_BASE_ADDR_SB,
};
+static int gr2d_init_opp_state(struct device *dev, struct gr2d *gr2d)
+{
+ struct dev_pm_opp *opp;
+ unsigned long rate;
+ int err;
+
+ /*
+ * If voltage regulator presents, then we could select the fastest
+ * clock rate, but driver doesn't support power management and
+ * frequency scaling yet, hence the top freq OPP will vote for a
+ * very high voltage that will produce lot's of heat. Let's select
+ * OPP for the current/default rate for now.
+ *
+ * Clock rate should be pre-initialized (i.e. it's non-zero) either
+ * by clock driver or by assigned clocks in a device-tree.
+ */
+ rate = clk_get_rate(gr2d->clk);
+
+ /* find suitable OPP for the clock rate supportable by SoC speedo ID */
+ opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+
+ /*
+ * dev_pm_opp_set_rate() doesn't search for a floor clock rate and it
+ * will error out if default clock rate is too high, i.e. unsupported
+ * by a SoC hardware version. Hence will find floor rate by ourselves.
+ */
+ if (opp == ERR_PTR(-ERANGE))
+ opp = dev_pm_opp_find_freq_floor(dev, &rate);
+
+ err = PTR_ERR_OR_ZERO(opp);
+ if (err) {
+ dev_err(dev, "failed to get OPP for %ld Hz: %d\n",
+ rate, err);
+ return err;
+ }
+
+ dev_pm_opp_put(opp);
+
+ /*
+ * First dummy rate-set initializes voltage vote by setting voltage
+ * in accordance to the clock rate. We need to do this because GR2D
+ * currently doesn't support power management and clock is permanently
+ * enabled.
+ */
+ err = dev_pm_opp_set_rate(dev, rate);
+ if (err) {
+ dev_err(dev, "failed to initialize OPP clock: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static void gr2d_deinit_opp_table(void *data)
+{
+ struct device *dev = data;
+ struct opp_table *opp_table;
+
+ opp_table = dev_pm_opp_get_opp_table(dev);
+ dev_pm_opp_of_remove_table(dev);
+ dev_pm_opp_put_supported_hw(opp_table);
+ dev_pm_opp_put_regulators(opp_table);
+ dev_pm_opp_put_opp_table(opp_table);
+}
+
+static int devm_gr2d_init_opp_table(struct device *dev, struct gr2d *gr2d)
+{
+ struct opp_table *opp_table, *hw_opp_table;
+ const char *rname = "core";
+ u32 hw_version;
+ int err;
+
+ /* voltage scaling is optional */
+ if (device_property_present(dev, "core-supply"))
+ opp_table = dev_pm_opp_set_regulators(dev, &rname, 1);
+ else
+ opp_table = dev_pm_opp_get_opp_table(dev);
+
+ if (IS_ERR(opp_table))
+ return dev_err_probe(dev, PTR_ERR(opp_table),
+ "failed to prepare OPP table\n");
+
+ if (gr2d->soc->version == 0x20)
+ hw_version = BIT(tegra_sku_info.soc_process_id);
+ else
+ hw_version = BIT(tegra_sku_info.soc_speedo_id);
+
+ hw_opp_table = dev_pm_opp_set_supported_hw(dev, &hw_version, 1);
+ err = PTR_ERR_OR_ZERO(hw_opp_table);
+ if (err) {
+ dev_err(dev, "failed to set supported HW: %d\n", err);
+ goto put_table;
+ }
+
+ /*
+ * OPP table presence is optional and we want the set_rate() of OPP
+ * API to work similarly to clk_set_rate() if table is missing in a
+ * device-tree. The add_table() errors out if OPP is missing in DT.
+ */
+ if (device_property_present(dev, "operating-points-v2")) {
+ err = dev_pm_opp_of_add_table(dev);
+ if (err) {
+ dev_err(dev, "failed to add OPP table: %d\n", err);
+ goto put_hw;
+ }
+
+ err = gr2d_init_opp_state(dev, gr2d);
+ if (err)
+ goto remove_table;
+ }
+
+ err = devm_add_action(dev, gr2d_deinit_opp_table, dev);
+ if (err)
+ goto remove_table;
+
+ dev_info(dev, "OPP HW ver. 0x%x\n", hw_version);
+
+ return 0;
+
+remove_table:
+ dev_pm_opp_of_remove_table(dev);
+put_hw:
+ dev_pm_opp_put_supported_hw(opp_table);
+put_table:
+ dev_pm_opp_put_regulators(opp_table);
+
+ return err;
+}
+
static int gr2d_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -209,6 +341,10 @@ static int gr2d_probe(struct platform_device *pdev)
return PTR_ERR(gr2d->clk);
}
+ err = devm_gr2d_init_opp_table(dev, gr2d);
+ if (err)
+ return dev_err_probe(dev, err, "failed to initialize OPP\n");
+
err = clk_prepare_enable(gr2d->clk);
if (err) {
dev_err(dev, "cannot turn on clock\n");
--
2.27.0
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