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Message-Id: <20201104234427.26477-18-digetx@gmail.com>
Date: Thu, 5 Nov 2020 02:44:14 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Alan Stern <stern@...land.harvard.edu>,
Peter Chen <Peter.Chen@....com>,
Mark Brown <broonie@...nel.org>,
Liam Girdwood <lgirdwood@...il.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Lee Jones <lee.jones@...aro.org>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>,
Ulf Hansson <ulf.hansson@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Marek Szyprowski <m.szyprowski@...sung.com>,
Peter Geis <pgwipeout@...il.com>,
Nicolas Chauvet <kwizart@...il.com>
Cc: linux-samsung-soc@...r.kernel.org, devel@...verdev.osuosl.org,
linux-usb@...r.kernel.org, linux-pwm@...r.kernel.org,
linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-media@...r.kernel.org, linux-tegra@...r.kernel.org
Subject: [PATCH v1 17/30] mmc: sdhci-tegra: Support OPP and core voltage scaling
Add OPP and SoC core voltage scaling support to the Tegra SDHCI driver.
This is required for enabling system-wide DVFS on older Tegra SoCs.
Tested-by: Peter Geis <pgwipeout@...il.com>
Tested-by: Nicolas Chauvet <kwizart@...il.com>
Signed-off-by: Dmitry Osipenko <digetx@...il.com>
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-tegra.c | 70 ++++++++++++++++++++++++++++++++--
2 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 310e546e5898..7d719c81b917 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -293,6 +293,7 @@ config MMC_SDHCI_TEGRA
depends on MMC_SDHCI_PLTFM
select MMC_SDHCI_IO_ACCESSORS
select MMC_CQHCI
+ select PM_OPP
help
This selects the Tegra SD/MMC controller. If you have a Tegra
platform with SD or MMC devices, say Y or M here.
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index ed12aacb1c73..964709a3ccd6 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -14,6 +14,7 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/pm_opp.h>
#include <linux/pinctrl/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
@@ -754,10 +755,15 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
+ struct device *dev = mmc_dev(host->mmc);
unsigned long host_clk;
- if (!clock)
- return sdhci_set_clock(host, clock);
+ /* disable clock and then remove OPP performance/voltage vote */
+ if (!clock) {
+ sdhci_set_clock(host, clock);
+ dev_pm_opp_set_rate(dev, clock);
+ return;
+ }
/*
* In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI
@@ -772,7 +778,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
* from clk_get_rate() is used.
*/
host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
- clk_set_rate(pltfm_host->clk, host_clk);
+ dev_pm_opp_set_rate(dev, host_clk);
tegra_host->curr_clk_rate = host_clk;
if (tegra_host->ddr_signaling)
host->max_clk = host_clk;
@@ -1558,6 +1564,60 @@ static int sdhci_tegra_add_host(struct sdhci_host *host)
return ret;
}
+static void sdhci_tegra_deinit_opp_table(void *data)
+{
+ struct device *dev = data;
+ struct opp_table *opp_table;
+
+ opp_table = dev_pm_opp_get_opp_table(dev);
+ dev_pm_opp_of_remove_table(dev);
+ dev_pm_opp_put_regulators(opp_table);
+ dev_pm_opp_put_opp_table(opp_table);
+}
+
+static int devm_sdhci_tegra_init_opp_table(struct device *dev)
+{
+ struct opp_table *opp_table;
+ const char *rname = "core";
+ int err;
+
+ /* voltage scaling is optional */
+ if (device_property_present(dev, "core-supply"))
+ opp_table = dev_pm_opp_set_regulators(dev, &rname, 1);
+ else
+ opp_table = dev_pm_opp_get_opp_table(dev);
+
+ if (IS_ERR(opp_table))
+ return dev_err_probe(dev, PTR_ERR(opp_table),
+ "failed to prepare OPP table\n");
+
+ /*
+ * OPP table presence is optional and we want the set_rate() of OPP
+ * API to work similarly to clk_set_rate() if table is missing in a
+ * device-tree. The add_table() errors out if OPP is missing in DT.
+ */
+ if (device_property_present(dev, "operating-points-v2")) {
+ err = dev_pm_opp_of_add_table(dev);
+ if (err) {
+ dev_err(dev, "failed to add OPP table: %d\n", err);
+ goto put_table;
+ }
+ }
+
+ err = devm_add_action(dev, sdhci_tegra_deinit_opp_table, dev);
+ if (err)
+ goto remove_table;
+
+ return 0;
+
+remove_table:
+ dev_pm_opp_of_remove_table(dev);
+put_table:
+ dev_pm_opp_put_regulators(opp_table);
+
+ return err;
+}
+
static int sdhci_tegra_probe(struct platform_device *pdev)
{
const struct of_device_id *match;
@@ -1621,6 +1681,10 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
goto err_power_req;
}
+ rc = devm_sdhci_tegra_init_opp_table(&pdev->dev);
+ if (rc)
+ goto err_parse_dt;
+
/*
* Tegra210 has a separate SDMMC_LEGACY_TM clock used for host
* timeout clock and SW can choose TMCLK or SDCLK for hardware
--
2.27.0
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