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Message-Id: <20201104234427.26477-5-digetx@gmail.com>
Date: Thu, 5 Nov 2020 02:44:01 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Alan Stern <stern@...land.harvard.edu>,
Peter Chen <Peter.Chen@....com>,
Mark Brown <broonie@...nel.org>,
Liam Girdwood <lgirdwood@...il.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Lee Jones <lee.jones@...aro.org>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>,
Ulf Hansson <ulf.hansson@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Marek Szyprowski <m.szyprowski@...sung.com>,
Peter Geis <pgwipeout@...il.com>,
Nicolas Chauvet <kwizart@...il.com>
Cc: linux-samsung-soc@...r.kernel.org, devel@...verdev.osuosl.org,
linux-usb@...r.kernel.org, linux-pwm@...r.kernel.org,
linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-media@...r.kernel.org, linux-tegra@...r.kernel.org
Subject: [PATCH v1 04/30] media: dt: bindings: tegra-vde: Document OPP and voltage regulator properties
Document new DVFS OPP table and voltage regulator properties of the
video decoder engine.
Signed-off-by: Dmitry Osipenko <digetx@...il.com>
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
index 602169b8aa19..9854fa9d3cd3 100644
--- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
+++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt
@@ -36,6 +36,16 @@ Optional properties:
- reset-names : Must include the following entries:
- mc
- iommus: Must contain phandle to the IOMMU device node.
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+- core-supply: Phandle to voltage regulator of the SoC "core" power domain.
+
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: One bitfield indicating:
+ On Tegra20: SoC process ID mask
+ On Tegra30+: SoC speedo ID mask
+
+ A bitwise AND is performed against the value and if any bit
+ matches, the OPP gets enabled.
Example:
@@ -61,4 +71,6 @@ video-codec@...1a000 {
reset-names = "vde", "mc";
resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
iommus = <&mc TEGRA_SWGROUP_VDE>;
+ operating-points-v2 = <&dvfs_opp_table>;
+ core-supply = <&vdd_core>;
};
--
2.27.0
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