linux-kernel - [PATCH 1/4] pinctrl: amd: fix incorrect way to disable debounce filter

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Date:   Thu,  5 Nov 2020 00:03:41 +0800
From:   Coiby Xu <coiby.xu@...il.com>
To:     Linus Walleij <linus.walleij@...aro.org>
Cc:     Hans de Goede <hdegoede@...hat.com>,
        linux-gpio@...r.kernel.org (open list:PIN CONTROL SUBSYSTEM),
        linux-kernel@...r.kernel.org (open list)
Subject: [PATCH 1/4] pinctrl: amd: fix incorrect way to disable debounce filter

The correct way to disable debounce filter is to clear bit 5 and 6
of the register.

Cc: Hans de Goede <hdegoede@...hat.com>
Message-ID: <df2c008b-e7b5-4fdd-42ea-4d1c62b52139@...hat.com>
Signed-off-by: Coiby Xu <coiby.xu@...il.com>
---
 drivers/pinctrl/pinctrl-amd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 9a760f5cd7ed..d6b2b4bd337c 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
 		} else {
-			pin_reg &= ~DB_CNTRl_MASK;
+			pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 			ret = -EINVAL;
 		}
 	} else {
 		pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 		pin_reg &= ~DB_TMR_OUT_MASK;
-		pin_reg &= ~DB_CNTRl_MASK;
+		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 	}
 	writel(pin_reg, gpio_dev->base + offset * 4);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
--
2.28.0