linux-kernel - [PATCH 3/6] dt-bindings: interrupt-controller: Add binding for the Microsemi Jaguar2 interrupt controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20201105171535.923570-4-gregory.clement@bootlin.com>
Date:   Thu,  5 Nov 2020 18:15:32 +0100
From:   Gregory CLEMENT <gregory.clement@...tlin.com>
To:     Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <maz@...nel.org>, linux-kernel@...r.kernel.org,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org
Cc:     Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Lars Povlsen <lars.povlsen@...rochip.com>,
        <Steen.Hegelund@...rochip.com>,
        Gregory CLEMENT <gregory.clement@...tlin.com>
Subject: [PATCH 3/6] dt-bindings: interrupt-controller: Add binding for the Microsemi Jaguar2 interrupt controller

Add the Device Tree binding documentation for the Microsemi Jaguar2
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.

Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
---
 .../interrupt-controller/mscc,ocelot-icpu-intr.txt         | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
index 42de86e023a6..916832064d64 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
@@ -1,11 +1,12 @@
 Microsemi Ocelot SoC ICPU Interrupt Controller
 
-Luton and Servals belong the same family as Ocelot: the VCoreIII family
+Luton, Servals and Jaguar 2 belong the same family as Ocelot: the
+VCoreIII family
 
 Required properties:
 
-- compatible : should be "mscc,ocelot-icpu-intr" or "mscc,luton-icpu-intr"
-               or "mscc,serval-icpu-intr"
+- compatible : should be "mscc,ocelot-icpu-intr", "mscc,luton-icpu-intr",
+               "mscc,serval-icpu-intr" or "mscc,jaguar2-icpu-intr"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.28.0