linux-kernel - Re: [PATCH v3 3/4] powercap: Add AMD Fam17h RAPL support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <2121012.oOYSSSs1xd@kreacher>
Date:   Thu, 05 Nov 2020 19:04:08 +0100
From:   "Rafael J. Wysocki" <rjw@...ysocki.net>
To:     Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>,
        Victor Ding <victording@...gle.com>
Cc:     Zhang Rui <rui.zhang@...el.com>,
        LKML <linux-kernel@...r.kernel.org>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Kim Phillips <kim.phillips@....com>, linux-pm@...r.kernel.org,
        Borislav Petkov <bp@...en8.de>,
        "H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...hat.com>,
        Joerg Roedel <jroedel@...e.de>,
        Kan Liang <kan.liang@...ux.intel.com>,
        Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        Sean Christopherson <sean.j.christopherson@...el.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Tony Luck <tony.luck@...el.com>,
        Vineela Tummalapalli <vineela.tummalapalli@...el.com>,
        x86@...nel.org
Subject: Re: [PATCH v3 3/4] powercap: Add AMD Fam17h RAPL support

On Thursday, November 5, 2020 6:14:01 PM CET Srinivas Pandruvada wrote:
> On Thu, 2020-11-05 at 14:53 +1100, Victor Ding wrote:
> > On Wed, Nov 4, 2020 at 1:17 PM Srinivas Pandruvada
> > <srinivas.pandruvada@...ux.intel.com> wrote:
> > > On Wed, 2020-11-04 at 12:43 +1100, Victor Ding wrote:
> > > > On Wed, Nov 4, 2020 at 4:09 AM Srinivas Pandruvada
> > > > <srinivas.pandruvada@...ux.intel.com> wrote:
> > > > > On Tue, 2020-11-03 at 17:10 +1100, Victor Ding wrote:
> > > > > > On Mon, Nov 2, 2020 at 12:39 PM Zhang Rui <
> > > > > > rui.zhang@...el.com>
> > > > > > wrote:
> > > > > > > On Tue, 2020-10-27 at 07:23 +0000, Victor Ding wrote:
> > > > > > > > This patch enables AMD Fam17h RAPL support for the power
> > > > > > > > capping
> > > > > > > > framework. The support is as per AMD Fam17h Model31h
> > > > > > > > (Zen2)
> > > > > > > > and
> > > > > > > > model 00-ffh (Zen1) PPR.
> > > > > > > > 
> > > > > > > > Tested by comparing the results of following two sysfs
> > > > > > > > entries
> > > > > > > > and
> > > > > > > > the
> > > > > > > > values directly read from corresponding MSRs via
> > > > > > > > /dev/cpu/[x]/msr:
> > > > > > > >   /sys/class/powercap/intel-rapl/intel-rapl:0/energy_uj
> > > > > > > >   /sys/class/powercap/intel-rapl/intel-rapl:0/intel-
> > > > > > > > rapl:0:0/energy_uj
> > > > > 
> > > > > Is this for just energy reporting? No capping of power?
> > > > Correct, the hardware does not support capping of power.
> > > I wonder if there is no capping, is this the right interface?
> > > Do you have specific user space, which cares about this?
> > We have tools that previously developed to measure energy status
> > on Intel via the powercap interface. Powercap is the only interface
> > allowing reading RAPL energy counters without requiring MSR access
> > privileges. We want to use these tools on AMD with minimal
> > modifications.
> > I believe the powercap interface should support these counters,
> > regardless of the use cases, mainly for two reasons:
> > 1. Powercap interface already supports monitoring-only power domains,
> > e.g. power limit is locked by BIOS or the (Intel) CPU does not expose
> > an
> > MSR for certain power domains. The latter is the exact situation on
> > AMD;
> > 2. As AMD has partially introduced the equivalent of Intel's RAPL, we
> > should leverage this opportunity to reduce the divergence in the
> > APIs. i.e.
> > OS as a hardware abstraction layer should allow users to use the same
> > set of APIs to access RAPL features if it issupported on both Intel
> > and AMD.
> > In this specific case, if users can query for Intel's RAPL counters
> > via
> > powercap, they should be able to do so as well for AMD's.
> > > I think these counters are already exposed via hwmon sysf.
> > Yes, they were introduced early this year. However, it is not the
> > same as
> > the counters exposed via powercap interface: powercap exposes the
> > actual value of the energy counters while hwmon adds an accumulation
> > layer on top.
> > In addition, I don't think Intel's RAPL counters are exposed via
> > hwmon;
> > therefore: 1. existing fine grade power monitoring tools are not
> > based on
> > hwmon; 2. new tools cannot query the same set of counters via the
> > same
> > API so that they have to actively maintain two sets of logic.
> 
> Fine with me.

OK, I'll queue up the series for 5.11 then if there are no other concerns.

Thanks!