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Message-ID: <87b00978-8d5d-1917-b801-e6a36f704fb3@arm.com>
Date:   Fri, 6 Nov 2020 19:33:46 +0000
From:   James Morse <james.morse@....com>
To:     Shiju Jose <shiju.jose@...wei.com>
Cc:     linux-edac@...r.kernel.org, linux-acpi@...r.kernel.org,
        linux-kernel@...r.kernel.org, bp@...en8.de, tony.luck@...el.com,
        rjw@...ysocki.net, lenb@...nel.org, rrichter@...vell.com,
        linuxarm@...wei.com, jonathan.cameron@...wei.com
Subject: Re: [RFC PATCH 0/4] EDAC/ghes: Add EDAC device for recording the CPU
 error count

Hi Shiju,

On 05/11/2020 17:42, Shiju Jose wrote:
> For the firmware-first error handling on ARM64 hardware platforms,
> CPU cache corrected error count is not recorded.
> Create an CPU EDAC device and device blocks for the CPU caches
> for this purpose. The EDAC device blocks  are created based on the
> CPU caches information represented in the ACPI PPTT.

Using the PPTT won't work on x86 systems. Can we use the core-code's common data to learn
about caches: struct cpu_cacheinfo and struct cacheinfo ?


Thanks,

James

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