linux-kernel - Re: [PATCH 2] Register read and writes tracing

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <a9de1928-d709-896f-ffa6-febc5d6d34c6@gmail.com>
Date:   Thu, 5 Nov 2020 19:58:31 -0800
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Prasad Sodagudi <psodagud@...eaurora.org>, rostedt@...dmis.org,
        mingo@...hat.com, keescook@...omium.org, catalin.marinas@....com,
        saiprakash.ranjan@...eaurora.org, will@...nel.org
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, gregkh@...uxfoundation.org,
        anton@...msg.org, arnd@...db.de, ccross@...roid.com,
        jbaron@...mai.com, jim.cromie@...il.com, joe@...ches.com,
        joel@...lfernandes.org
Subject: Re: [PATCH 2] Register read and writes tracing



On 11/5/2020 6:56 PM, Prasad Sodagudi wrote:
> This patch series adds register read/write event tracing
> support. Qualcomm team tried upstreaming the register
> trace buffer solution - [1] with pstore and dynamic debug
> feature but that patch series didn't merge. I have followed
> Steve suggestion from -[2] and used tracepoint_enabled() API.
> 
> [1] - https://patchwork.kernel.org/project/linux-arm-msm/cover/cover.1536430404.git.saiprakash.ranjan@codeaurora.org/
> [2] - https://lore.kernel.org/lkml/20200928105501.7e29df65@oasis.local.home/ 
> 
> Qualcomm teams uses these logs for debugging various issues
> in the product life cycle and hopping that this logging
> would help other silicon vendors as this is generic approach.

There is not anything arm64 specific here other than where you have
hooked into the low-level I/O accessors, you could consider adding this
as a generic facility to other architectures as well.

Also, have you looked at making mmiotrace less x86 specific and more
generic?
-- 
Florian