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Message-ID: <1604654884-30339-4-git-send-email-claudiu.beznea@microchip.com>
Date:   Fri, 6 Nov 2020 11:27:56 +0200
From:   Claudiu Beznea <claudiu.beznea@...rochip.com>
To:     <mturquette@...libre.com>, <sboyd@...nel.org>,
        <nicolas.ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
        <ludovic.desroches@...rochip.com>, <robh+dt@...nel.org>
CC:     <eugen.hristev@...rochip.com>, <linux-clk@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: [PATCH v3 03/11] clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT

From: Eugen Hristev <eugen.hristev@...rochip.com>

Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
from phandle in DT.

Suggested-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@...rochip.com>
[claudiu.beznea@...rochip.com: adapt commit message, add CPU PLL]
Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
---
 drivers/clk/at91/sama7g5.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 7ef7963126b6..d3c3469d47d9 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -117,7 +117,8 @@ static const struct {
 		  .p = "cpupll_fracck",
 		  .l = &pll_layout_divpmc,
 		  .t = PLL_TYPE_DIV,
-		  .c = 1, },
+		  .c = 1,
+		  .eid = PMC_CPUPLL, },
 	},
 
 	[PLL_ID_SYS] = {
@@ -131,7 +132,8 @@ static const struct {
 		  .p = "syspll_fracck",
 		  .l = &pll_layout_divpmc,
 		  .t = PLL_TYPE_DIV,
-		  .c = 1, },
+		  .c = 1,
+		  .eid = PMC_SYSPLL, },
 	},
 
 	[PLL_ID_DDR] = {
-- 
2.7.4

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