linux-kernel - [PATCH 3/3] ARM: dts: imx50-kobo-aura: Enable eKTF2132 touchscreen

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Message-Id: <20201106112412.390724-4-j.neuschaefer@gmx.net>
Date:   Fri,  6 Nov 2020 12:24:12 +0100
From:   Jonathan Neuschäfer <j.neuschaefer@....net>
To:     linux-input@...r.kernel.org
Cc:     Dmitry Torokhov <dmitry.torokhov@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        Jonathan Neuschäfer <j.neuschaefer@....net>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 3/3] ARM: dts: imx50-kobo-aura: Enable eKTF2132 touchscreen

The Kobo Aura has an eKTF2132 touchscreen controller.

Although the vendor kernel toggles a reset pin (GPIO5-12) during the
startup sequence, the touchscreen works without it.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@....net>
---

This patch requires "[PATCH] ARM: dts: imx50-kobo-aura: Add 'grp' suffix
to pinctrl node names" in order to apply cleanly.
(https://lore.kernel.org/lkml/20201031210729.2804471-1-j.neuschaefer@gmx.net/)
---
 arch/arm/boot/dts/imx50-kobo-aura.dts | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts
index b2fbee60271f2..82ce8c43be867 100644
--- a/arch/arm/boot/dts/imx50-kobo-aura.dts
+++ b/arch/arm/boot/dts/imx50-kobo-aura.dts
@@ -120,7 +120,14 @@ &i2c1 {
 	pinctrl-0 = <&pinctrl_i2c1>;
 	status = "okay";

-	/* TODO: ektf2132 touch controller at 0x15 */
+	touchscreen@15 {
+		reg = <0x15>;
+		compatible = "elan,ektf2132";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ts>;
+		power-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+		interrupts-extended = <&gpio5 13 IRQ_TYPE_EDGE_FALLING>;
+	};
 };

 &i2c2 {
@@ -240,6 +247,13 @@ MX50_PAD_SD3_D7__ESDHC3_DAT7		0x1d4
 		>;
 	};

+	pinctrl_ts: tsgrp {
+		fsl,pins = <
+			MX50_PAD_CSPI_MOSI__GPIO4_9		0x0
+			MX50_PAD_SD2_D5__GPIO5_13		0x0
+		>;
+	};
+
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			MX50_PAD_UART2_TXD__UART2_TXD_MUX	0x1e4
--
2.28.0