lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Sun, 08 Nov 2020 23:52:11 +0100 From: Thomas Gleixner <tglx@...utronix.de> To: David Woodhouse <dwmw2@...radead.org> Cc: Jason Gunthorpe <jgg@...dia.com>, "Tian\, Kevin" <kevin.tian@...el.com>, "Jiang\, Dave" <dave.jiang@...el.com>, Bjorn Helgaas <helgaas@...nel.org>, "vkoul\@kernel.org" <vkoul@...nel.org>, "Dey\, Megha" <megha.dey@...el.com>, "maz\@kernel.org" <maz@...nel.org>, "bhelgaas\@google.com" <bhelgaas@...gle.com>, "alex.williamson\@redhat.com" <alex.williamson@...hat.com>, "Pan\, Jacob jun" <jacob.jun.pan@...el.com>, "Raj\, Ashok" <ashok.raj@...el.com>, "Liu\, Yi L" <yi.l.liu@...el.com>, "Lu\, Baolu" <baolu.lu@...el.com>, "Kumar\, Sanjay K" <sanjay.k.kumar@...el.com>, "Luck\, Tony" <tony.luck@...el.com>, "jing.lin\@intel.com" <jing.lin@...el.com>, "Williams\, Dan J" <dan.j.williams@...el.com>, "kwankhede\@nvidia.com" <kwankhede@...dia.com>, "eric.auger\@redhat.com" <eric.auger@...hat.com>, "parav\@mellanox.com" <parav@...lanox.com>, "rafael\@kernel.org" <rafael@...nel.org>, "netanelg\@mellanox.com" <netanelg@...lanox.com>, "shahafs\@mellanox.com" <shahafs@...lanox.com>, "yan.y.zhao\@linux.intel.com" <yan.y.zhao@...ux.intel.com>, "pbonzini\@redhat.com" <pbonzini@...hat.com>, "Ortiz\, Samuel" <samuel.ortiz@...el.com>, "Hossain\, Mona" <mona.hossain@...el.com>, "dmaengine\@vger.kernel.org" <dmaengine@...r.kernel.org>, "linux-kernel\@vger.kernel.org" <linux-kernel@...r.kernel.org>, "linux-pci\@vger.kernel.org" <linux-pci@...r.kernel.org>, "kvm\@vger.kernel.org" <kvm@...r.kernel.org> Subject: Re: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection On Sun, Nov 08 2020 at 22:09, David Woodhouse wrote: >> On Fri, Nov 06 2020 at 09:14, Jason Gunthorpe wrote: >>> On Fri, Nov 06, 2020 at 09:48:34AM +0000, Tian, Kevin wrote: >>> For instance you could put a "disable IMS" flag in the ACPI tables, in >>> the config space of the emuulated root port, or any other areas that >>> clearly belong to the platform. >>> >>> The OS logic would be >>> - If no IMS information found then use IMS (Bare metal) >>> - If the IMS disable flag is found then >>> - If (future) hypercall available and the OS knows how to use it >>> then use IMS >>> - If no hypercall found, or no OS knowledge, fail IMS >> >> That does not work because an older hypervisor would not have that >> disable flag and the guest kernel would assume to be on bare metal (if >> no other indicators are there). > > In the absence of a forward-thinking design from Intel perhaps we could Just to be fair the AMD interrupt remapping is not any better in that regard. Thanks, tglx
Powered by blists - more mailing lists