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Message-ID: <20201109163143.tm5gjz77rr734lm5@linutronix.de>
Date: Mon, 9 Nov 2020 17:31:43 +0100
From: Sebastian Andrzej Siewior <bigeasy@...utronix.de>
To: Daniel Wagner <wagi@...om.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
LKML <linux-kernel@...r.kernel.org>,
linux-rt-users <linux-rt-users@...r.kernel.org>,
Steven Rostedt <rostedt@...dmis.org>
Subject: Re: [ANNOUNCE] v5.10-rc2-rt4
On 2020-11-09 15:37:03 [+0100], Daniel Wagner wrote:
> > this looks odd. So rt1 has 415, rt2 has 399 and rt3 has 420 so lets say
> > it is the same. And then rt4 should reduce it to 340. The only part that
> > could have some influence is the are the highmem/kmap patches. But for
> > ARM64 these are still a nop and in both cases kmap_atomic() disables
> > migrate & page-fault.
> >
> > Are you sure those numbers always reproducible and not something that
> > goes wrong and sometimes it is captured at 300us and sometimes 400us.
>
> These test run only very short with hackbench as worlkload (5 minutes).
> Though I running these tests now for more than year with v4.4-rt and
> some times the newer -rt releases and I've never seen the latency
> numbers above 200us unless something was broken. Given that 5 minutes is
> not really long, I'll let those test run for longer to see if I get the
> same results when they run for one hour.
oki.
> > I've been staring at the code of signaltest on Friday and I might need
> > to stare longer to figure out what it does.
>
> I hear you. Anyway, I gave the current head a run with lazy preemption
> disabled as you asked for.
…
> 5.10.0-rc2-rt4 vs 5.10.0-rc2-rt4(lazy preemption disabled)
>
> 0_cyclicdeadline t2-max-latency pass/pass 274.00/ 61.00 349.18%
So the value went from 274us to 61us after disabling lazy-preempt?
> cyclicdeadline seems heavily affected by the change.
Sebastian
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