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Message-ID: <fd85ff4f-150f-958a-231a-a95848cd9af4@amd.com>
Date: Mon, 9 Nov 2020 14:41:48 -0600
From: Tom Lendacky <thomas.lendacky@....com>
To: Arvind Sankar <nivedita@...m.mit.edu>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Andy Lutomirski <luto@...nel.org>,
Peter Zijlstra <peterz@...radead.org>
Cc: x86@...nel.org, linux-kernel@...r.kernel.org,
Borislav Petkov <bp@...en8.de>
Subject: Re: [PATCH] x86/mm/sme: Fix definition of PMD_FLAGS_DEC_WP
On 11/9/20 11:35 AM, Arvind Sankar wrote:
> The PAT bit is in different locations for 4k and 2M/1G page table
> entries.
>
> Add a definition for _PAGE_LARGE_CACHE_MASK to represent the three
> caching bits (PWT, PCD, PAT), similar to _PAGE_CACHE_MASK for 4k pages,
> and use it in the definition of PMD_FLAGS_DEC_WP to get the correct PAT
> index for write-protected pages.
>
> Remove a duplication definition of _PAGE_PAT_LARGE.
>
> Signed-off-by: Arvind Sankar <nivedita@...m.mit.edu>
Fixes: tag?
Tested-by: Tom Lendacky <thomas.lendacky@....com>
> ---
> arch/x86/include/asm/pgtable_types.h | 3 +--
> arch/x86/mm/mem_encrypt_identity.c | 4 ++--
> 2 files changed, 3 insertions(+), 4 deletions(-)
>
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