linux-kernel - Re: [PATCH] clk: hisilicon: Add clock driver for hi3559A SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <202011100629.CfeOqGdM-lkp@intel.com>
Date:   Tue, 10 Nov 2020 06:59:48 +0800
From:   kernel test robot <lkp@...el.com>
To:     Dongjiu Geng <gengdongjiu@...wei.com>, mturquette@...libre.com,
        sboyd@...nel.org, robh+dt@...nel.org, devicetree@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Cc:     kbuild-all@...ts.01.org, clang-built-linux@...glegroups.com
Subject: Re: [PATCH] clk: hisilicon: Add clock driver for hi3559A SoC

Hi Dongjiu,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on v5.10-rc3 next-20201109]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Dongjiu-Geng/clk-hisilicon-Add-clock-driver-for-hi3559A-SoC/20201109-220823
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm-randconfig-r001-20201109 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 09ec07827b1128504457a93dee80b2ceee1af600)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm cross compiling tool for clang build
        # apt-get install binutils-arm-linux-gnueabi
        # https://github.com/0day-ci/linux/commit/4c47c8e369dc38c57f55055c51d0c22565d472e6
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Dongjiu-Geng/clk-hisilicon-Add-clock-driver-for-hi3559A-SoC/20201109-220823
        git checkout 4c47c8e369dc38c57f55055c51d0c22565d472e6
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>

All warnings (new ones prefixed by >>):

>> drivers/clk/hisilicon/clk-hi3559a.c:467:6: warning: no previous prototype for function 'hisi_clk_register_pll' [-Wmissing-prototypes]
   void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
        ^
   drivers/clk/hisilicon/clk-hi3559a.c:467:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
   ^
   static 
   1 warning generated.

vim +/hisi_clk_register_pll +467 drivers/clk/hisilicon/clk-hi3559a.c

   466	
 > 467	void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
   468				   int nums, struct hisi_clock_data *data)
   469	{
   470		void __iomem *base = data->base;
   471		int i;
   472	
   473		for (i = 0; i < nums; i++) {
   474			struct hi3559av100_clk_pll *p_clk = NULL;
   475			struct clk *clk = NULL;
   476			struct clk_init_data init;
   477	
   478			p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
   479			if (!p_clk)
   480				return;
   481	
   482			init.name = clks[i].name;
   483			init.flags = 0;
   484			init.parent_names =
   485				(clks[i].parent_name ? &clks[i].parent_name : NULL);
   486			init.num_parents = (clks[i].parent_name ? 1 : 0);
   487			init.ops = &clk_pll_ops;
   488	
   489			p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
   490			p_clk->frac_shift = clks[i].frac_shift;
   491			p_clk->frac_width = clks[i].frac_width;
   492			p_clk->postdiv1_shift = clks[i].postdiv1_shift;
   493			p_clk->postdiv1_width = clks[i].postdiv1_width;
   494			p_clk->postdiv2_shift = clks[i].postdiv2_shift;
   495			p_clk->postdiv2_width = clks[i].postdiv2_width;
   496	
   497			p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
   498			p_clk->fbdiv_shift = clks[i].fbdiv_shift;
   499			p_clk->fbdiv_width = clks[i].fbdiv_width;
   500			p_clk->refdiv_shift = clks[i].refdiv_shift;
   501			p_clk->refdiv_width = clks[i].refdiv_width;
   502			p_clk->hw.init = &init;
   503	
   504			clk = clk_register(NULL, &p_clk->hw);
   505			if (IS_ERR(clk)) {
   506				kfree(p_clk);
   507				pr_err("%s: failed to register clock %s\n",
   508				       __func__, clks[i].name);
   509				continue;
   510			}
   511	
   512			data->clk_data.clks[clks[i].id] = clk;
   513		}
   514	}
   515	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

Download attachment ".config.gz" of type "application/gzip" (35216 bytes)