linux-kernel - Re: [PATCH 6/9] phy: cadence: sierra: Don't configure if any plls are already locked

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 09 Nov 2020 09:39:33 +0100
From:   Philipp Zabel <p.zabel@...gutronix.de>
To:     Kishon Vijay Abraham I <kishon@...com>,
        Vinod Koul <vkoul@...nel.org>, Rob Herring <robh+dt@...nel.org>
Cc:     Swapnil Kashinath Jakhade <sjakhade@...ence.com>,
        Milind Parab <mparab@...ence.com>,
        Yuti Suresh Amonkar <yamonkar@...ence.com>,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 6/9] phy: cadence: sierra: Don't configure if any plls
 are already locked

On Tue, 2020-11-03 at 09:25 +0530, Kishon Vijay Abraham I wrote:
> From: Faiz Abbas <faiz_abbas@...com>
> 
> Serdes lanes might be shared between multiple cores in some usecases
> and its not possible to lock PLLs for both the lanes independently
> by the two cores. This requires a bootloader to configure both the
> lanes at early boot time.
> 
> To handle this case, skip all configuration if any of the plls are
> already locked. This is done by adding an already_configured flag
> and using it to gate every register access as well as any phy_ops.
> 
> Signed-off-by: Faiz Abbas <faiz_abbas@...com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
> ---
>  drivers/phy/cadence/phy-cadence-sierra.c | 127 ++++++++++++++---------
>  1 file changed, 78 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
> index e08548417bce..145e42837b7b 100644
> --- a/drivers/phy/cadence/phy-cadence-sierra.c
> +++ b/drivers/phy/cadence/phy-cadence-sierra.c
> @@ -364,6 +364,10 @@ static const struct phy_ops ops = {
>  	.owner		= THIS_MODULE,
>  };
>  
> +static const struct phy_ops noop_ops = {
> +	.owner		= THIS_MODULE,
> +};
> +
>  static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
>  				    struct device_node *child)
>  {
> @@ -477,6 +481,49 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
>  	return 0;
>  }
>  
> +static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
> +				      struct device *dev)
> +{
> +	struct clk *clk;
> +	int ret;
> +
> +	sp->clk = devm_clk_get_optional(dev, "phy_clk");
> +	if (IS_ERR(sp->clk)) {
> +		dev_err(dev, "failed to get clock phy_clk\n");
> +		return PTR_ERR(sp->clk);
> +	}
> +
> +	sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");

While you're at it, please use devm_reset_control_get_exclusive() here
and ...

> +	if (IS_ERR(sp->phy_rst)) {
> +		dev_err(dev, "failed to get reset\n");
> +		return PTR_ERR(sp->phy_rst);
> +	}
> +
> +	sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb");

... devm_reset_control_get_optional_exclusive() here.

regards
Philipp