linux-kernel - Re: [RFC PATCH v3 9/9] arm64: dts: lx2160a: fix FlexSPI clock

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Date:   Mon, 09 Nov 2020 10:43:03 +0100
From:   Michael Walle <michael@...le.cc>
To:     Vladimir Oltean <vladimir.oltean@....com>
Cc:     linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>, Leo Li <leoyang.li@....com>,
        "Y.b. Lu" <yangbo.lu@....com>, Xiaowei Bao <xiaowei.bao@....com>,
        Ashish Kumar <ashish.kumar@....com>
Subject: Re: [RFC PATCH v3 9/9] arm64: dts: lx2160a: fix FlexSPI clock

Am 2020-11-08 22:21, schrieb Vladimir Oltean:
> On Sun, Nov 08, 2020 at 07:51:13PM +0100, Michael Walle wrote:
>> Now that we have a proper driver for the FlexSPI interface use it. 
>> This
>> will fix SCK frequency switching on Layerscape SoCs.
>> 
>> Signed-off-by: Michael Walle <michael@...le.cc>
>> ---
>> Thanks to Vladimir Oltean, this was partially tested on a LX2160A RDB. 
>> But
>> this patch is marked as RFC nonetheless, because there is too much
>> difference in the clock tree between LS1028A and LX2160A. It would be 
>> nice
>> if someone could test it and add a Tested-by.
> 
> You want someone to probe the SCK frequency?

No not really, just a thorough test.

> I expect that if frequency
> switching works on LS1028A, and the lx2160a_flexspi_divs table is
> correct (which, based on the documentation for 
> FlexSPICR1[FlexSPI_CLK_DIV],
> it is), then it would work on LX2160A too?

The switching should work. Finding out wether it is correct can be 
checked
by reading the raw register value, i.e. 01E0_0900h. But the parent clock 
is
what is bothering me a little. Getting that wrong would lead to a wrong 
SCK
output frequency albeit the divider is set to a correct value.

> Is there a simple test that can be made in order to trivially determine
> whether the frequencies are correct?

We already found out that there seems to be kind of a saturation with
higher frequencies, i.e. octal SPI bus is capable of a much higher
throughput but we only achieve 50MB/s. I'd have expected a much higher
datarate (I mean it is advertised as high performance and it uses a 8 
bit
wide databus..). But anyway, it might make sense to go the other way, 
i.e.
find out the max datathroughput at lower frequencies and look if it 
makes
sense. Assuming no DDR, the throughput should be around your frequency. 
For
example, having 4 MHz should result in 4MB/s data throughput.

OTOH we already saw that after linux booted - with the current device 
tree
which has a setting of 50MHz max SCK frequency - the programmed divider 
by
my driver is the same as the former setting (0x13, div-by-32); so this 
series
doesn't change the SCK frequency.

-michael