linux-kernel - Re: [PATCH 2/2] drm/msm/a5xx: Clear shadow on suspend

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Date:   Tue, 10 Nov 2020 11:46:24 -0700
From:   Jordan Crouse <jcrouse@...eaurora.org>
To:     Rob Clark <robdclark@...il.com>
Cc:     dri-devel@...ts.freedesktop.org,
        Rob Clark <robdclark@...omium.org>,
        Sean Paul <sean@...rly.run>, David Airlie <airlied@...ux.ie>,
        Daniel Vetter <daniel@...ll.ch>,
        "Kristian H. Kristensen" <hoegsberg@...gle.com>,
        Eric Anholt <eric@...olt.net>,
        "Gustavo A. R. Silva" <gustavoars@...nel.org>,
        Emil Velikov <emil.velikov@...labora.com>,
        "open list:DRM DRIVER FOR MSM ADRENO GPU" 
        <linux-arm-msm@...r.kernel.org>,
        "open list:DRM DRIVER FOR MSM ADRENO GPU" 
        <freedreno@...ts.freedesktop.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] drm/msm/a5xx: Clear shadow on suspend

On Tue, Nov 10, 2020 at 10:44:00AM -0800, Rob Clark wrote:
> From: Rob Clark <robdclark@...omium.org>
> 
> Similar to the previous patch, clear shadow on suspend to avoid timeouts
> waiting for ringbuffer space.
> 
> Fixes: 8907afb476ac ("drm/msm: Allow a5xx to mark the RPTR shadow as privileged")
> Signed-off-by: Rob Clark <robdclark@...omium.org>

Reviewed-by: Jordan Crouse <jcrouse@...eaurora.org>
> ---
>  drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index b0005ccd81c6..8fa5c917d017 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -1206,7 +1206,9 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
>  static int a5xx_pm_suspend(struct msm_gpu *gpu)
>  {
>  	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> +	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
>  	u32 mask = 0xf;
> +	int i, ret;
>  
>  	/* A510 has 3 XIN ports in VBIF */
>  	if (adreno_is_a510(adreno_gpu))
> @@ -1226,7 +1228,15 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
>  	gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000);
>  	gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000);
>  
> -	return msm_gpu_pm_suspend(gpu);
> +	ret = msm_gpu_pm_suspend(gpu);
> +	if (ret)
> +		return ret;
> +
> +	if (a5xx_gpu->has_whereami)
> +		for (i = 0; i < gpu->nr_rings; i++)
> +			a5xx_gpu->shadow[i] = 0;
> +
> +	return 0;
>  }
>  
>  static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
> -- 
> 2.28.0
> 

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