linux-kernel - Re: [PATCH 1/2] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite

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Message-ID: <9f4ae806ba3d283caaab37f0f2aa7ea0@codeaurora.org>
Date:   Wed, 11 Nov 2020 00:28:36 +0530
From:   Sibi Sankar <sibis@...eaurora.org>
To:     Doug Anderson <dianders@...omium.org>
Cc:     Bjorn Andersson <bjorn.andersson@...aro.org>,
        Matthias Kaehlcke <mka@...omium.org>,
        Andy Gross <agross@...nel.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>,
        Evan Green <evgreen@...omium.org>,
        Rob Herring <robh+dt@...nel.org>,
        Stephen Boyd <swboyd@...omium.org>
Subject: Re: [PATCH 1/2] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling
 on SC7180-lite

On 2020-10-17 04:29, Doug Anderson wrote:
> Hi,
> 
> On Thu, Oct 15, 2020 at 10:53 AM Sibi Sankar <sibis@...eaurora.org> 
> wrote:
>> 
>> Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC
>> since the gold cores only support frequencies upto 2.1 GHz.
>> 
>> Signed-off-by: Sibi Sankar <sibis@...eaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sc7180-lite.dtsi | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
>> new file mode 100644
>> index 000000000000..cff50275cfe1
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
>> @@ -0,0 +1,14 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * SC7180 lite device tree source
>> + *
>> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +&cpu6_opp11 {
>> +       opp-peak-kBps = <8532000 22425600>;
>> +};
>> +
>> +&cpu6_opp12 {
>> +       opp-peak-kBps = <8532000 23347200>;
>> +};
> 
> I guess this is OK, but something about it smells just a little
> strange...  I guess:
> 
> a) There's suddenly a big jump from opp10 to opp11.  You don't use
> 7216000 at all anymore.
> 
> b) The fact that we need to do this at all feels like a sign that
> somehow this wasn't designed quite right.
> 
> Just brainstorming a bit: If the higher memory rate wasn't useful for
> OPP11/12 on the non-lite version of the chip, why are they useful for
> that OPP on the lite version?  I guess you're just trying to eek out
> the last little bits of performance once the cpufreq is maxed out?  It

Doug,

Really sorry about the delayed response,
running power tests and getting some fuse
info took longer than expected. Yes the
mapping table as expected is a trade off
between power/perf and it has been determined
that lite version would meet the power
numbers even with the high memory votes
at lower freqs.

1900800000 --> opp-peak-kBps = <7216000 22425600>;
1996800000 --> opp-peak-kBps = <7216000 22425600>;
2112000000 --> opp-peak-kBps = <8532000 23347200>;

^^ is the new recommendation from the perf/power
QC teams for lite and is expected to have better
power numbers with similar perf.

> almost feels like a better way to do this (though it wouldn't be
> monotonically increasing anymore so it wouldn't actually work) would
> be to have a few "OPP" points at the top where the cpufreq stops
> increasing and all you do is increase the memory frequency.
> 
> c) In theory we're supposed to be able to probe whether we're on the
> normal, lite, or pro version, right?  Anyway we could tweak this in
> code so we don't have to know to include the right dtsi file?

Yes we can determine f_max by reading speed_bin
efuse values or by OSM table traversal (though
latter looks more like a hack) and use that
along with opp-supported-hw to identity supported
opps.

I would prefer If we can avoid doing ^^ if
we can get away with overloading the votes
in dt but I don't have any strong opinions
on this. So let me know how you want it done
and I'll fix it up accordingly in the next
re-spin.

> 
> 
> -Doug

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