linux-kernel - Re: [EXTERNAL] [tip: x86/apic] x86/io_apic: Cleanup trigger/polarity helpers

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Message-ID: <45B3C20C-3BBB-40F3-8A7B-EB20EDD0706F@infradead.org>
Date:   Tue, 10 Nov 2020 19:21:38 +0000
From:   David Woodhouse <dwmw2@...radead.org>
To:     Thomas Gleixner <tglx@...utronix.de>,
        Tom Lendacky <thomas.lendacky@....com>,
        Borislav Petkov <bp@...en8.de>
CC:     linux-kernel@...r.kernel.org, x86 <x86@...nel.org>,
        Qian Cai <cai@...hat.com>, Joerg Roedel <joro@...tes.org>
Subject: Re: [EXTERNAL] [tip: x86/apic] x86/io_apic: Cleanup trigger/polarity helpers



On 10 November 2020 18:56:17 GMT, Thomas Gleixner <tglx@...utronix.de> wrote:
>On Tue, Nov 10 2020 at 18:50, Thomas Gleixner wrote:
>> On Tue, Nov 10 2020 at 16:33, David Woodhouse wrote:
>>> If I could get post-5.5 kernels to boot at all with the AMD IOMMU
>>> enabled, I'd have a go at throwing that together now...
>>
>> It can share the dmar domain code. Let me frob something.
>
>Not much to share there and I can't access my AMD machine at the
>moment. Something like the untested below should work.

Does it even need its own irqdomain? Can it not just allocate directly from the vector domain then program its own register directly based on the irq_cfg?


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