linux-kernel - [PATCH 07/19] arm64: dts: allwinner: A100: Add PMU mode

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Message-Id: <20201110040553.1381-8-frank@allwinnertech.com>
Date:   Tue, 10 Nov 2020 12:05:41 +0800
From:   Frank Lee <frank@...winnertech.com>
To:     vkoul@...nel.org, robh+dt@...nel.org, mripard@...nel.org,
        wens@...e.org, ulf.hansson@...aro.org, kishon@...com,
        wim@...ux-watchdog.org, linux@...ck-us.net,
        dan.j.williams@...el.com, linus.walleij@...aro.org,
        wsa+renesas@...g-engineering.com, dianders@...omium.org,
        marex@...x.de, colin.king@...onical.com, rdunlap@...radead.org,
        krzk@...nel.org, gregkh@...uxfoundation.org, megous@...ous.com,
        rikard.falkeborn@...il.com, dmaengine@...r.kernel.org,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-mmc@...r.kernel.org,
        linux-watchdog@...r.kernel.org, linux-gpio@...r.kernel.org,
        tiny.windzz@...il.com
Cc:     Yangtao Li <frank@...winnertech.com>
Subject: [PATCH 07/19] arm64: dts: allwinner: A100: Add PMU mode

From: Yangtao Li <frank@...winnertech.com>

Add the Performance Monitoring Unit (PMU) device tree node to the A100
.dtsi, which tells DT users which interrupts are triggered by PMU overflow
events on each core.

Signed-off-by: Yangtao Li <frank@...winnertech.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index c34ed8045363..01ff53b5a7a8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -25,21 +25,21 @@ cpu0: cpu@0 {
 			enable-method = "psci";
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x1>;
 			enable-method = "psci";
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x2>;
 			enable-method = "psci";
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x3>;
@@ -47,6 +47,15 @@ cpu@3 {
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
-- 
2.28.0