linux-kernel - Re: [PATCH v2 1/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver

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Date:   Tue, 10 Nov 2020 15:18:39 +0100
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Cc:     Bjorn Andersson <bjorn.andersson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Andy Gross <agross@...nel.org>,
        MSM <linux-arm-msm@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver

On Fri, Nov 6, 2020 at 12:08 PM Srinivas Kandagatla
<srinivas.kandagatla@...aro.org> wrote:

> Some more detail of wiring of this additional pin-controller IP:
>
> This IP is an additional pinctrl block on top the existing SoC TLMM
> pin-controller (Audio) pins.
>
> The hw setup looks like:
>
> TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13]
>
> However SoC TLMM pin-controller can only be touched for use of those
> pins in GPIO mode and non gpio mode is completely handled by the LPASS
> LPI pinctrl block. Apart from this slew rate is also available in this
> block for certain pins which are connected to SLIMbus or SoundWire Bus.

OK put this in the commit message, good to know!

I gues the pins are not quite "GPIO" at this point, instead they are
turned into LPASS pins?

> Normally we would not expect these pins to be touched by SoC TLMM
> pin-controller as these pins are used for audio usecase and the control
> is always with LPASS LPI controller. There are additional bits to
> configure/enforce this in SoC TLMM block!

If you start to use IRQs they might become hierarchical WRT the
TLMM. But no IRQ support yet, so...

Yours,
Linus Walleij