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Message-ID: <CAMpxmJUfRi8g1B7ufya4py+ta-jnCWew+QR94O-HCDuuWyiLdA@mail.gmail.com>
Date: Tue, 10 Nov 2020 15:24:02 +0100
From: Bartosz Golaszewski <bgolaszewski@...libre.com>
To: Andy Shevchenko <andy.shevchenko@...il.com>
Cc: Bartosz Golaszewski <brgl@...ev.pl>,
Linus Walleij <linus.walleij@...aro.org>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
Jan Kiszka <jan.kiszka@...mens.com>,
David Laight <David.Laight@...lab.com>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 6/7] gpio: exar: switch to using regmap
On Tue, Nov 10, 2020 at 3:11 PM Andy Shevchenko
<andy.shevchenko@...il.com> wrote:
>
> On Tue, Nov 10, 2020 at 2:35 PM Bartosz Golaszewski <brgl@...ev.pl> wrote:
>
> ...
>
> > struct exar_gpio_chip {
> > struct gpio_chip gpio_chip;
> > - struct mutex lock;
>
> > + struct regmap *regs;
>
> Leaving the same name is a call for potential troubles.
>
> > int index;
> > - void __iomem *regs;
> > char name[20];
> > unsigned int first_pin;
> > };
>
> ...
>
> > +static const struct regmap_config exar_regmap_config = {
> > + .name = "exar-gpio",
> > + .reg_bits = 8,
> > + .val_bits = 8,
> > +};
>
> Looking at the crash, are you sure this is a comprehensive description?
> Maybe it requires something like stride or so?
>
This is what I'm looking at ATM. Looking at the datasheet[1], there
are no breaks in the registers so the default stride of 1 should be
fine as is the value bits width of 8. I think that I got the address
width wrong though. Should be 16 bits probably.
Jan: could you change reg_bits to 16 and try again?
Bartosz
[1] https://www.maxlinear.com/ds/xr17v352.pdf
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