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Message-Id: <160529906735.20198.6590820523478984130.b4-ty@arm.com>
Date: Fri, 13 Nov 2020 20:26:17 +0000
From: Catalin Marinas <catalin.marinas@....com>
To: will@...nel.org, sudeep.holla@....com, mark.rutland@....com,
Ionela Voinescu <ionela.voinescu@....com>
Cc: morten.rasmussen@....com, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 0/3] arm64: cppc: add FFH support using AMUs
On Fri, 6 Nov 2020 12:53:31 +0000, Ionela Voinescu wrote:
> Many thanks for everyone's review.
>
> This series adds support for CPPC's delivered and reference performance
> counters through the FFH methods by using the AMU equivalent core and
> constant cycle counters.
>
> This support is added in patch 3/3, while the first 2 patches generalise
> the existing AMU counter read and validation functionality to be reused
> for this usecase.
>
> [...]
Applied to arm64 (for-next/cppc-ffh), thanks!
[1/3] arm64: wrap and generalise counter read functions
https://git.kernel.org/arm64/c/4b9cf23c179a
[2/3] arm64: split counter validation function
https://git.kernel.org/arm64/c/bc3b6562a1ac
[3/3] arm64: implement CPPC FFH support using AMUs
https://git.kernel.org/arm64/c/68c5debcc06d
I also applied the irq_disabled() abort as per Mark's comments:
https://git.kernel.org/arm64/c/74490422522d
--
Catalin
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