lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAMhs-H_qFpVv3KK5Bc4igrj7VffZSmAAT=sM8PSyY7H0-SV1yg@mail.gmail.com>
Date:   Fri, 13 Nov 2020 06:32:55 +0100
From:   Sergio Paracuellos <sergio.paracuellos@...il.com>
To:     Chuanhong Guo <gch981213@...il.com>
Cc:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        John Crispin <john@...ozen.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Weijie Gao <hackpascal@...il.com>, jiaxun.yang@...goat.com,
        "open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>,
        "open list:MIPS" <linux-mips@...r.kernel.org>,
        "open list:STAGING SUBSYSTEM" <devel@...verdev.osuosl.org>
Subject: Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate
 driver for MT7621

On Fri, Nov 13, 2020 at 1:40 AM Chuanhong Guo <gch981213@...il.com> wrote:
>
> On Thu, Nov 12, 2020 at 1:23 PM Sergio Paracuellos
> <sergio.paracuellos@...il.com> wrote:
> >
> > To avoid weird behaviour because of some drivers are
> > not using properly clocks we have the CLK_IGNORED_UNUSED, which as you
> > can see is currently being used in my code. Using that all seems to
> > work as expected as it is now.
>
> The whole point of having a clock gate driver is to gate unused
> clocks to save (maybe a tiny bit of) power. It's other peripheral
> drivers' fault that it doesn't enable clocks properly and we shouldn't
> just work-around the problem in the clock driver by disallowing auto
> clock gating.
>

Totally agreed with what you are saying here but I don't really think
using the flag is a workaround. It is just a way to ensure no
regressions occurred until all drivers are adapted and also having all
of them enabled is the behaviour. For me adapt the rest of driver code
 should be a different patch set after this driver is properly
finished and mainlined.

> --
> Regards,
> Chuanhong Guo

Best regards,
     Sergio Paracuellos

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ