Message-ID: <CACRpkdYta9FG-aYN1KbpFrsvO_ZGNTX=CJqiL8uL3e7QQQR4Gg@mail.gmail.com>
Date:   Fri, 13 Nov 2020 14:22:43 +0100
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Linus Torvalds <torvalds@...ux-foundation.org>
Cc:     linux-kernel <linux-kernel@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Coiby Xu <coiby.xu@...il.com>
Subject: [GIT PULL] pin control fixes for the v5.10 series

Hi Linus,

here is a bunch of pin control fixes for the v5.10 kernel
series.

Nothing in particular to say about it, because they are all
driver fixes.

I'm happy that some AMD driver fixes are appearing, it's
been an undermaintained driver, and laptops have suffered.

Please pull it in!

Yours,
Linus Walleij

The following changes since commit 3650b228f83adda7e5ee532e2b90429c03f7b9ec:

  Linux 5.10-rc1 (2020-10-25 15:14:11 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
tags/pinctrl-v5.10-2

for you to fetch changes up to dadfab0fbf0173da6e24c8322b69083fef03033d:

  Merge tag 'intel-pinctrl-v5.10-2' of
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes
(2020-11-10 15:35:41 +0100)

----------------------------------------------------------------
Pin control fixes for the v5.10 series:

- Two fixes to the Intel pin controller drivers: fixing
  pull resistance bias.

- Fix some invalid SSI pins on the Ingenic pin controller.

- Make sure the clock is enabled when requesting interrupts
  from the Rockchip GPIO controller.

- Make sure IRQs are mapped when looking up the IRQ for
  a GPIO line on the Rockchip GPIO Write.

- Two regmap initialization fixes for the MCP23s08.

- Fix a GPI-only prefix function problem on the Aspeed pin
  controller.

- Disable the debounce filter correctly on the AMD
  pin controller.

- Correct the timer clock setting for the AMD debounce
  timer.

- Make the Qualcomm pin controller more cautious around the
  handling of PDC-related GPIO interrupts.

- Fix the interrupt map in the Qualcomm SM8250 pin controller.

----------------------------------------------------------------
Andy Shevchenko (4):
      pinctrl: intel: Fix 2 kOhm bias which is 833 Ohm
      pinctrl: intel: Set default bias in case no particular value given
      pinctrl: mcp23s08: Use full chunk of memory for regmap configuration
      pinctrl: mcp23s08: Print error message when regmap init fails

Billy Tsai (1):
      pinctrl: aspeed: Fix GPI only function problem.

Bjorn Andersson (1):
      pinctrl: qcom: sm8250: Specify PDC map

Coiby Xu (2):
      pinctrl: amd: fix incorrect way to disable debounce filter
      pinctrl: amd: use higher precision for 512 RtcClk

Jianqun Xu (2):
      pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
      pinctrl: rockchip: create irq mapping in gpio_to_irq

Linus Walleij (1):
      Merge tag 'intel-pinctrl-v5.10-2' of
git://git.kernel.org/.../pinctrl/intel into fixes

Maulik Shah (1):
      pinctrl: qcom: Move clearing pending IRQ to
.irq_request_resources callback

Paul Cercueil (1):
      pinctrl: ingenic: Fix invalid SSI pins

 drivers/pinctrl/aspeed/pinctrl-aspeed.c |  7 ++--
 drivers/pinctrl/intel/pinctrl-intel.c   | 40 +++++++++++++-----
 drivers/pinctrl/pinctrl-amd.c           |  6 +--
 drivers/pinctrl/pinctrl-ingenic.c       | 72 ++++++++++++++++-----------------
 drivers/pinctrl/pinctrl-mcp23s08_spi.c  |  4 +-
 drivers/pinctrl/pinctrl-rockchip.c      | 30 +++++++-------
 drivers/pinctrl/qcom/pinctrl-msm.c      | 32 +++++++++------
 drivers/pinctrl/qcom/pinctrl-sm8250.c   | 18 +++++++++
 8 files changed, 127 insertions(+), 82 deletions(-)

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