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Message-ID: <20201114211837.GB12197@araj-mobl1.jf.intel.com>
Date: Sat, 14 Nov 2020 13:18:37 -0800
From: "Raj, Ashok" <ashok.raj@...el.com>
To: Christoph Hellwig <hch@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>,
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Ashok Raj <ashok.raj@...el.com>
Subject: Re: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection
On Sat, Nov 14, 2020 at 10:34:30AM +0000, Christoph Hellwig wrote:
> On Thu, Nov 12, 2020 at 11:42:46PM +0100, Thomas Gleixner wrote:
> > DMI vendor name is pretty good final check when the bit is 0. The
> > strings I'm aware of are:
> >
> > QEMU, Bochs, KVM, Xen, VMware, VMW, VMware Inc., innotek GmbH, Oracle
> > Corporation, Parallels, BHYVE, Microsoft Corporation
> >
> > which is not complete but better than nothing ;)
>
> Which is why I really think we need explicit opt-ins for "native"
> SIOV handling and for paravirtualized SIOV handling, with the kernel
> not offering support at all without either or a manual override on
> the command line.
opt-in by device or kernel? The way we are planning to support this is:
Device support for IMS - Can discover in device specific means
Kernel support for IMS. - Supported by IOMMU driver.
each driver can check
if (dev_supports_ims() && iommu_supports_ims()) {
/* Then IMS is supported in the platform.*/
}
until we have vIOMMU support or a hypercall, iommu_supports_ims() will
check if X86_FEATURE_HYPERVISOR in addition to the platform id's Thomas
mentioned. or on intel platform check for cap.caching_mode=1 and return false.
When we add support for getting a native interrupt handle then we will plumb that
appropriately.
Does this match what you wanted?
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