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Message-Id: <20201116175508.51943-2-zhouyanjie@wanyeetech.com>
Date: Tue, 17 Nov 2020 01:55:07 +0800
From: 周琰杰 (Zhou Yanjie)
<zhouyanjie@...yeetech.com>
To: tsbogend@...ha.franken.de, robh+dt@...nel.org, paul@...pouillou.net
Cc: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, ak@...ux.intel.com, krzk@...nel.org,
ebiederm@...ssion.com, hns@...delico.com, paulburton@...nel.org,
nixiaoming@...wei.com, dongsheng.qiu@...enic.com,
aric.pzqi@...enic.com, rick.tyliu@...enic.com,
yanfei.li@...enic.com, sernia.zhou@...mail.com,
zhenwenjin@...il.com
Subject: [PATCH v2 1/2] MIPS: Ingenic: Add missing nodes for Ingenic SoCs and boards.
1.Add OTG/OTG PHY/RNG nodes for JZ4780, CGU/OTG nodes for CI20.
2.Add OTG/OTG PHY/RNG/OST nodes for X1000, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1000-Neo.
3.Add OTG/OTG PHY/DTRNG/OST nodes for X1830, SSI/CGU/OST/OTG/SC16IS752
nodes for CU1830-Neo.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@...mail.com>
Tested by: H. Nikolaus Schaller <hns@...delico.com> # CI20/jz4780
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
---
Notes:
v1->v2:
1.Add the otg_power node for otg_phy's vcc_supply.
2.Move assigned-clocks in the otg node into the cgu node.
3.Move the position of the SSI node.
arch/mips/boot/dts/ingenic/ci20.dts | 45 +++++++++++++++++++--
arch/mips/boot/dts/ingenic/cu1000-neo.dts | 62 ++++++++++++++++++++++++++---
arch/mips/boot/dts/ingenic/cu1830-neo.dts | 66 ++++++++++++++++++++++++++++---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 45 ++++++++++++++++++++-
arch/mips/boot/dts/ingenic/x1000.dtsi | 56 +++++++++++++++++++++++++-
arch/mips/boot/dts/ingenic/x1830.dtsi | 58 ++++++++++++++++++++++++++-
6 files changed, 313 insertions(+), 19 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 75f5bfbf2c37..8877c62609de 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -69,9 +69,11 @@
eth0_power: fixedregulator@0 {
compatible = "regulator-fixed";
+
regulator-name = "eth0_power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+
gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
enable-active-high;
};
@@ -83,16 +85,39 @@
wlan0_power: fixedregulator@1 {
compatible = "regulator-fixed";
+
regulator-name = "wlan0_power";
+
gpio = <&gpb 19 GPIO_ACTIVE_LOW>;
enable-active-high;
};
+
+ otg_power: fixedregulator@2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "otg_power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpf 14 GPIO_ACTIVE_LOW>;
+ enable-active-high;
+ };
};
&ext {
clock-frequency = <48000000>;
};
+&cgu {
+ /*
+ * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
+ * precision.
+ */
+ assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>;
+ assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>;
+ assigned-clock-rates = <48000000>;
+};
+
&mmc0 {
status = "okay";
@@ -396,6 +421,16 @@
status = "okay";
};
+&otg_phy {
+ status = "okay";
+
+ vcc-supply = <&otg_power>;
+};
+
+&otg {
+ status = "okay";
+};
+
&pinctrl {
pins_uart0: uart0 {
function = "uart0";
@@ -489,7 +524,11 @@
};
&tcu {
- /* 3 MHz for the system timer and clocksource */
- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
- assigned-clock-rates = <3000000>, <3000000>;
+ /*
+ * 750 kHz for the system timer and 3 MHz for the clocksource,
+ * use channel #0 for the system timer, #1 for the clocksource.
+ */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_OST>;
+ assigned-clock-rates = <750000>, <3000000>, <3000000>;
};
diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
index 22a1066d637b..f98cf029efc3 100644
--- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
+++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
@@ -3,7 +3,7 @@
#include "x1000.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/ingenic,tcu.h>
+#include <dt-bindings/clock/ingenic,sysost.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@@ -31,6 +31,42 @@
};
};
+ ssi: spi-gpio {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-chipselects = <1>;
+
+ mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
+
+ status = "okay";
+
+ spi-max-frequency = <50000000>;
+
+ sc16is752: expander@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>; /* CE0 */
+ spi-max-frequency = <4000000>;
+
+ clocks = <&exclk_sc16is752>;
+
+ interrupt-parent = <&gpc>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ exclk_sc16is752: sc16is752 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+ };
+ };
+
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";
@@ -43,13 +79,19 @@
clock-frequency = <24000000>;
};
-&tcu {
+&cgu {
+ /*
+ * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
+ * precision.
+ */
+ assigned-clocks = <&cgu X1000_CLK_RTC>;
+ assigned-clock-parents = <&cgu X1000_CLK_RTCLK>;
+};
+
+&ost {
/* 1500 kHz for the system timer and clocksource */
- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
+ assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
-
- /* Use channel #0 for the system timer channel #2 for the clocksource */
- ingenic,pwm-channels-mask = <0xfa>;
};
&uart2 {
@@ -135,6 +177,14 @@
};
};
+&otg_phy {
+ status = "okay";
+};
+
+&otg {
+ status = "okay";
+};
+
&pinctrl {
pins_uart2: uart2 {
function = "uart2";
diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
index 640f96c00d63..cfcb40edb7d9 100644
--- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
+++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
@@ -3,7 +3,7 @@
#include "x1830.dtsi"
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/ingenic,tcu.h>
+#include <dt-bindings/clock/ingenic,sysost.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
@@ -31,6 +31,42 @@
};
};
+ ssi0: spi-gpio {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-chipselects = <1>;
+
+ mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
+
+ status = "okay";
+
+ spi-max-frequency = <50000000>;
+
+ sc16is752: expander@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>; /* CE0 */
+ spi-max-frequency = <4000000>;
+
+ clocks = <&exclk_sc16is752>;
+
+ interrupt-parent = <&gpb>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ exclk_sc16is752: sc16is752 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+ };
+ };
+
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";
@@ -43,13 +79,19 @@
clock-frequency = <24000000>;
};
-&tcu {
+&cgu {
+ /*
+ * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
+ * precision.
+ */
+ assigned-clocks = <&cgu X1830_CLK_RTC>;
+ assigned-clock-parents = <&cgu X1830_CLK_RTCLK>;
+};
+
+&ost {
/* 1500 kHz for the system timer and clocksource */
- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
+ assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
-
- /* Use channel #0 for the system timer channel #2 for the clocksource */
- ingenic,pwm-channels-mask = <0xfa>;
};
&uart1 {
@@ -73,6 +115,10 @@
};
};
+&dtrng {
+ status = "okay";
+};
+
&msc0 {
status = "okay";
@@ -135,6 +181,14 @@
};
};
+&otg_phy {
+ status = "okay";
+};
+
+&otg {
+ status = "okay";
+};
+
&pinctrl {
pins_uart1: uart1 {
function = "uart1";
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index dfb5a7e1bb21..8d01feef7ff5 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -61,13 +61,34 @@
};
cgu: jz4780-cgu@...00000 {
- compatible = "ingenic,jz4780-cgu";
+ compatible = "ingenic,jz4780-cgu", "simple-mfd";
reg = <0x10000000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000000 0x100>;
+
+ #clock-cells = <1>;
clocks = <&ext>, <&rtc>;
clock-names = "ext", "rtc";
- #clock-cells = <1>;
+ otg_phy: usb-phy@3c {
+ compatible = "ingenic,jz4780-phy";
+ reg = <0x3c 0x10>;
+
+ clocks = <&cgu JZ4780_CLK_OTG1>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ rng: rng@d8 {
+ compatible = "ingenic,jz4780-rng";
+ reg = <0xd8 0x8>;
+
+ status = "disabled";
+ };
};
tcu: timer@...02000 {
@@ -494,4 +515,24 @@
status = "disabled";
};
+
+ otg: usb@...00000 {
+ compatible = "ingenic,jz4780-otg", "snps,dwc2";
+ reg = <0x13500000 0x40000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <21>;
+
+ clocks = <&cgu JZ4780_CLK_UHC>;
+ clock-names = "otg";
+
+ phys = <&otg_phy>;
+ phy-names = "usb2-phy";
+
+ g-rx-fifo-size = <768>;
+ g-np-tx-fifo-size = <256>;
+ g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
+
+ status = "disabled";
+ };
};
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index 1f1f896dd1f7..aac9dedaf334 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -52,13 +52,47 @@
};
cgu: x1000-cgu@...00000 {
- compatible = "ingenic,x1000-cgu";
+ compatible = "ingenic,x1000-cgu", "simple-mfd";
reg = <0x10000000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000000 0x100>;
#clock-cells = <1>;
clocks = <&exclk>, <&rtclk>;
clock-names = "ext", "rtc";
+
+ otg_phy: usb-phy@3c {
+ compatible = "ingenic,x1000-phy";
+ reg = <0x3c 0x10>;
+
+ clocks = <&cgu X1000_CLK_OTGPHY>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ rng: rng@d8 {
+ compatible = "ingenic,x1000-rng";
+ reg = <0xd8 0x8>;
+
+ status = "disabled";
+ };
+ };
+
+ ost: timer@...00000 {
+ compatible = "ingenic,x1000-ost";
+ reg = <0x12000000 0x3c>;
+
+ #clock-cells = <1>;
+
+ clocks = <&cgu X1000_CLK_OST>;
+ clock-names = "ost";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
};
tcu: timer@...02000 {
@@ -323,4 +357,24 @@
status = "disabled";
};
};
+
+ otg: usb@...00000 {
+ compatible = "ingenic,x1000-otg", "snps,dwc2";
+ reg = <0x13500000 0x40000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <21>;
+
+ clocks = <&cgu X1000_CLK_OTG>;
+ clock-names = "otg";
+
+ phys = <&otg_phy>;
+ phy-names = "usb2-phy";
+
+ g-rx-fifo-size = <768>;
+ g-np-tx-fifo-size = <256>;
+ g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
+
+ status = "disabled";
+ };
};
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index b05dac3ae308..b21c93057356 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -52,13 +52,40 @@
};
cgu: x1830-cgu@...00000 {
- compatible = "ingenic,x1830-cgu";
+ compatible = "ingenic,x1830-cgu", "simple-mfd";
reg = <0x10000000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000000 0x100>;
#clock-cells = <1>;
clocks = <&exclk>, <&rtclk>;
clock-names = "ext", "rtc";
+
+ otg_phy: usb-phy@3c {
+ compatible = "ingenic,x1830-phy";
+ reg = <0x3c 0x10>;
+
+ clocks = <&cgu X1830_CLK_OTGPHY>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ ost: timer@...00000 {
+ compatible = "ingenic,x1830-ost", "ingenic,x1000-ost";
+ reg = <0x12000000 0x3c>;
+
+ #clock-cells = <1>;
+
+ clocks = <&cgu X1830_CLK_OST>;
+ clock-names = "ost";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <4>;
};
tcu: timer@...02000 {
@@ -236,6 +263,15 @@
status = "disabled";
};
+ dtrng: trng@...72000 {
+ compatible = "ingenic,x1830-dtrng";
+ reg = <0x10072000 0xc>;
+
+ clocks = <&cgu X1830_CLK_DTRNG>;
+
+ status = "disabled";
+ };
+
pdma: dma-controller@...20000 {
compatible = "ingenic,x1830-dma";
reg = <0x13420000 0x400
@@ -311,4 +347,24 @@
status = "disabled";
};
};
+
+ otg: usb@...00000 {
+ compatible = "ingenic,x1830-otg", "snps,dwc2";
+ reg = <0x13500000 0x40000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <21>;
+
+ clocks = <&cgu X1830_CLK_OTG>;
+ clock-names = "otg";
+
+ phys = <&otg_phy>;
+ phy-names = "usb2-phy";
+
+ g-rx-fifo-size = <768>;
+ g-np-tx-fifo-size = <256>;
+ g-tx-fifo-size = <256 256 256 256 256 256 256 512>;
+
+ status = "disabled";
+ };
};
--
2.11.0
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