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Message-ID: <3f2239fe-367a-16de-fcb5-543d39f34c22@intel.com>
Date: Mon, 16 Nov 2020 08:36:36 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: Matthew Wilcox <willy@...radead.org>
Cc: "Kirill A. Shutemov" <kirill@...temov.name>,
Peter Zijlstra <peterz@...radead.org>,
kan.liang@...ux.intel.com, mingo@...nel.org, acme@...nel.org,
mark.rutland@....com, alexander.shishkin@...ux.intel.com,
jolsa@...hat.com, eranian@...gle.com, christophe.leroy@...roup.eu,
npiggin@...il.com, linuxppc-dev@...ts.ozlabs.org,
mpe@...erman.id.au, will@...nel.org, aneesh.kumar@...ux.ibm.com,
sparclinux@...r.kernel.org, davem@...emloft.net,
catalin.marinas@....com, linux-arch@...r.kernel.org,
linux-kernel@...r.kernel.org, ak@...ux.intel.com,
kirill.shutemov@...ux.intel.com
Subject: Re: [PATCH 0/5] perf/mm: Fix PERF_SAMPLE_*_PAGE_SIZE
On 11/16/20 8:32 AM, Matthew Wilcox wrote:
>>
>> That's really the best we can do from software without digging into
>> microarchitecture-specific events.
> I mean this is perf. Digging into microarch specific events is what it
> does ;-)
Yeah, totally.
But, if we see a bunch of 4k TLB hit events, it's still handy to know
that those 4k TLB hits originated from a 2M page table entry. This
series just makes sure that perf has the data about the page table
mapping sizes regardless of what the microarchitecture does with it.
I'm just saying we need to make the descriptions in this perf feature
specifically about the page tables, not the TLB.
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