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Message-ID: <20201116165707.GI3121392@hirez.programming.kicks-ass.net>
Date: Mon, 16 Nov 2020 17:57:07 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Dave Hansen <dave.hansen@...el.com>
Cc: Matthew Wilcox <willy@...radead.org>,
"Kirill A. Shutemov" <kirill@...temov.name>,
kan.liang@...ux.intel.com, mingo@...nel.org, acme@...nel.org,
mark.rutland@....com, alexander.shishkin@...ux.intel.com,
jolsa@...hat.com, eranian@...gle.com, christophe.leroy@...roup.eu,
npiggin@...il.com, linuxppc-dev@...ts.ozlabs.org,
mpe@...erman.id.au, will@...nel.org, aneesh.kumar@...ux.ibm.com,
sparclinux@...r.kernel.org, davem@...emloft.net,
catalin.marinas@....com, linux-arch@...r.kernel.org,
linux-kernel@...r.kernel.org, ak@...ux.intel.com,
kirill.shutemov@...ux.intel.com
Subject: Re: [PATCH 0/5] perf/mm: Fix PERF_SAMPLE_*_PAGE_SIZE
On Mon, Nov 16, 2020 at 08:36:36AM -0800, Dave Hansen wrote:
> On 11/16/20 8:32 AM, Matthew Wilcox wrote:
> >>
> >> That's really the best we can do from software without digging into
> >> microarchitecture-specific events.
> > I mean this is perf. Digging into microarch specific events is what it
> > does ;-)
>
> Yeah, totally.
Sure, but the automatic promotion/demotion of TLB sizes is not visible
if you don't know what you startd out with.
> But, if we see a bunch of 4k TLB hit events, it's still handy to know
> that those 4k TLB hits originated from a 2M page table entry. This
> series just makes sure that perf has the data about the page table
> mapping sizes regardless of what the microarchitecture does with it.
This.
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