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Message-ID: <f0d35834054cc1ac77ac0e6b68e84d62de3c48f7.camel@infradead.org>
Date: Tue, 17 Nov 2020 12:19:53 +0000
From: David Woodhouse <dwmw2@...radead.org>
To: Thomas Gleixner <tglx@...utronix.de>,
"Eric W. Biederman" <ebiederm@...ssion.com>,
Bjorn Helgaas <helgaas@...nel.org>
Cc: "Guilherme G. Piccoli" <gpiccoli@...onical.com>, lukas@...ner.de,
linux-pci@...r.kernel.org, kernelfans@...il.com,
andi@...stfloor.org, hpa@...or.com, bhe@...hat.com, x86@...nel.org,
okaya@...nel.org, mingo@...hat.com, jay.vosburgh@...onical.com,
dyoung@...hat.com, gavin.guo@...onical.com, bp@...en8.de,
bhelgaas@...gle.com, Guowen Shan <gshan@...hat.com>,
"Rafael J. Wysocki" <rjw@...ysocki.net>, kernel@...ccoli.net,
kexec@...ts.infradead.org, linux-kernel@...r.kernel.org,
ddstreet@...onical.com, vgoyal@...hat.com
Subject: Re: [PATCH 1/3] x86/quirks: Scan all busses for early PCI quirks
On Tue, 2020-11-17 at 10:53 +0100, Thomas Gleixner wrote:
> But that does not solve the problem either simply because then the IOMMU
> will catch the rogue MSIs and you get an interrupt storm on the IOMMU
> error interrupt.
Not if you can tell the IOMMU to stop reporting those errors.
We can easily do it per-device for DMA errors; not quite sure what
granularity we have for interrupts. Perhaps the Intel IOMMU only lets
you set the Fault Processing Disable bit per IRTE entry, and you still
get faults for Compatibility Format interrupts? Not sure about AMD...
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