linux-kernel - RE: [PATCH 3/3] mmc: rtsx: Add SD Express mode support for RTS5261

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Message-ID: <cc6872ac36d14ddc928ee02acc434cae@realsil.com.cn>
Date:   Tue, 17 Nov 2020 02:09:07 +0000
From:   冯锐 <rui_feng@...lsil.com.cn>
To:     Christoph Hellwig <hch@....de>,
        Ulf Hansson <ulf.hansson@...aro.org>
CC:     Arnd Bergmann <arnd@...db.de>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>
Subject: RE: [PATCH 3/3] mmc: rtsx: Add SD Express mode support for RTS5261


> -----Original Message-----
> From: Christoph Hellwig [mailto:hch@....de]
> Sent: Friday, November 13, 2020 12:42 AM
> To: Ulf Hansson <ulf.hansson@...aro.org>
> Cc: Christoph Hellwig <hch@....de>; 冯锐 <rui_feng@...lsil.com.cn>; Arnd
> Bergmann <arnd@...db.de>; Greg Kroah-Hartman
> <gregkh@...uxfoundation.org>; Linux Kernel Mailing List
> <linux-kernel@...r.kernel.org>; linux-mmc@...r.kernel.org
> Subject: Re: [PATCH 3/3] mmc: rtsx: Add SD Express mode support for RTS5261
> 
> On Fri, Oct 23, 2020 at 02:12:19PM +0200, Ulf Hansson wrote:
> > SD spec mentions the write-protect switch on SD cards, while uSD cards
> > doesn't have one. In general, host drivers implement support for it
> > via a dedicated GPIO line routed to one of the pins in the SD slot.
> >
> > In this SD controller case, which is based upon PCI, it works a bit
> > differently, as the state of the write protect pin is managed through
> > the PCI interface.
> >
> > If I understand you correctly, you are saying that the controller
> > should be able to communicate (upwards to the block layer) its known
> > write protect state for the corresponding NVMe device, during
> > initialization?
> 
> I got an answer form a member of the SD commitee, and the answer is:
> 
> "The SD specification define that case very clearly as following.
> If card’s access is restricted through one of the SD unique features – PSWD
> Lock/Unlock,  Temporary or Permanent WP (TWP or PWP) or CPRM  then if
> access attempt is done through its NVMe interface the card will restrict the
> access
> and respond with Access denied.    The access restriction shall be removed
> through the SD protocol/interface before being able to access the card through
> the NVMe.
> That is defined as following in the section 8.1.6  of the SD7.0 onward."
> 
> Note that if you look at the spec this means only rejecting NVMe commands
> that write dta for the write protect pin.
> 
You may misunderstand my meaning. The "WP" I mean is the "Mechanical Write Protect Switch" and
it's defined in section 4.3.6 of The SD specification. The "WP" you mentioned is "Card Internal Write Protect".
They are two different "WP". For "Mechanical Write Protect Switch" , The SD specification define as following.
"It is the responsibility of the host to protect the card. The position of the write protect switch is unknown to the
Internal circuitry of the card."
So we use legacy SD interface to handle the card which is "WP" by "Mechanical Write Protect Switch".