lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20201118103517.GA4556@piout.net>
Date:   Wed, 18 Nov 2020 11:35:17 +0100
From:   Alexandre Belloni <alexandre.belloni@...tlin.com>
To:     Gregory CLEMENT <gregory.clement@...tlin.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <maz@...nel.org>, linux-kernel@...r.kernel.org,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Lars Povlsen <lars.povlsen@...rochip.com>,
        Steen.Hegelund@...rochip.com
Subject: Re: [PATCH v3 2/5] dt-bindings: interrupt-controller: Add binding
 for few Microsemi interrupt controllers

Hello,

On 16/11/2020 17:24:24+0100, Gregory CLEMENT wrote:
> Add the Device Tree binding documentation for the Microsemi Jaguar2,
> Luton and Serval interrupt controller that is part of the ICPU. It is
> connected directly to the MIPS core interrupt controller.
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
> ---
>  .../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml  | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
> index 3a537635a859..5483ed7062ba 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
> @@ -21,7 +21,11 @@ properties:
>    compatible:
>      items:
>        - enum:
> +          - mscc,jaguar2-icpu-intr
> +          - mscc,luton-icpu-intr
>            - mscc,ocelot-icpu-intr
> +          - mscc,serval-icpu-intr
> +

Spurious blank line

>  
>    '#interrupt-cells':
>      const: 1
> -- 
> 2.29.2
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ