linux-kernel - Re: [PATCH] mmc: sdhci-of-arasan: Add pinctrl support to the driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <f3a6f0e5-6bca-d85f-9330-bf73151ee956@xilinx.com>
Date:   Wed, 18 Nov 2020 14:49:00 +0100
From:   Michal Simek <michal.simek@...inx.com>
To:     Manish Narani <manish.narani@...inx.com>,
        <michal.simek@...inx.com>, <adrian.hunter@...el.com>,
        <ulf.hansson@...aro.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-mmc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <git@...inx.com>
Subject: Re: [PATCH] mmc: sdhci-of-arasan: Add pinctrl support to the driver



On 18. 11. 20 7:21, Manish Narani wrote:
> Driver should be able to handle optional pinctrl setting.
> 
> Signed-off-by: Michal Simek <michal.simek@...inx.com>
> Signed-off-by: Manish Narani <manish.narani@...inx.com>
> ---
>  drivers/mmc/host/sdhci-of-arasan.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 829ccef87426..f788cc9d5914 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -23,6 +23,7 @@
>  #include <linux/regmap.h>
>  #include <linux/of.h>
>  #include <linux/firmware/xlnx-zynqmp.h>
> +#include <linux/pinctrl/consumer.h>
>  
>  #include "cqhci.h"
>  #include "sdhci-pltfm.h"
> @@ -135,6 +136,8 @@ struct sdhci_arasan_clk_data {
>   * @clk_ops:		Struct for the Arasan Controller Clock Operations.
>   * @soc_ctl_base:	Pointer to regmap for syscon for soc_ctl registers.
>   * @soc_ctl_map:	Map to get offsets into soc_ctl registers.
> + * @pinctrl:		Per-device pin control state holder.
> + * @pins_default:	Pinctrl state for a device.
>   * @quirks:		Arasan deviations from spec.
>   */
>  struct sdhci_arasan_data {
> @@ -149,6 +152,8 @@ struct sdhci_arasan_data {
>  
>  	struct regmap	*soc_ctl_base;
>  	const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
> +	struct pinctrl	*pinctrl;
> +	struct pinctrl_state *pins_default;
>  	unsigned int	quirks;
>  
>  /* Controller does not have CD wired and will not function normally without */
> @@ -1619,6 +1624,25 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>  		goto unreg_clk;
>  	}
>  
> +	sdhci_arasan->pinctrl = devm_pinctrl_get(&pdev->dev);
> +	if (!IS_ERR(sdhci_arasan->pinctrl)) {
> +		sdhci_arasan->pins_default =
> +			pinctrl_lookup_state(sdhci_arasan->pinctrl,
> +					     PINCTRL_STATE_DEFAULT);
> +		if (IS_ERR(sdhci_arasan->pins_default)) {
> +			dev_err(&pdev->dev, "Missing default pinctrl config\n");
> +			ret = PTR_ERR(sdhci_arasan->pins_default);
> +			goto unreg_clk;
> +		}
> +
> +		ret = pinctrl_select_state(sdhci_arasan->pinctrl,
> +					   sdhci_arasan->pins_default);
> +		if (ret) {
> +			dev_err(&pdev->dev, "could not select default state\n");
> +			goto unreg_clk;
> +		}
> +	}
> +
>  	sdhci_arasan->phy = ERR_PTR(-ENODEV);
>  	if (of_device_is_compatible(pdev->dev.of_node,
>  				    "arasan,sdhci-5.1")) {
> 

Ulf: Is there any need to describe in binding doc? I mean all txt based
binding have it described. But not quite sure if there is a need to
describe it in yaml if only default option is supported.
And when this is optional it should be fine also for others SOC.

For patch itself.

Acked-by: Michal Simek <michal.simek@...inx.com>

Thanks,
Michal