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Date: Thu, 19 Nov 2020 10:39:48 -0800 From: Benjamin Fair <benjaminfair@...gle.com> To: Tomer Maimon <tmaimon77@...il.com> Cc: Joel Stanley <joel@....id.au>, Arnd Bergmann <arnd@...db.de>, olof@...om.net, arm@...nel.org, soc@...nel.org, avifishman70@...il.com, Rob Herring <robh+dt@...nel.org>, mark.rutland@....com, Nancy Yuen <yuenn@...gle.com>, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, OpenBMC Maillist <openbmc@...ts.ozlabs.org> Subject: Re: [PATCH v1] ARM: dts: add Nuvoton NPCM730 device tree On Thu, 19 Nov 2020 at 00:00, Tomer Maimon <tmaimon77@...il.com> wrote: > > Add Nuvoton NPCM730 SoC device tree. > > The Nuvoton NPCN730 SoC is a part of the > Nuvoton NPCM7xx SoCs family. > > Signed-off-by: Tomer Maimon <tmaimon77@...il.com> Reviewed-by: Benjamin Fair <benjaminfair@...gle.com> > > --- > arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi > > diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > new file mode 100644 > index 000000000000..86ec12ec2b50 > --- /dev/null > +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > @@ -0,0 +1,44 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2020 Nuvoton Technology > + > +#include "nuvoton-common-npcm7xx.dtsi" > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "nuvoton,npcm750-smp"; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <0>; > + next-level-cache = <&l2>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <1>; > + next-level-cache = <&l2>; > + }; > + }; > + > + soc { > + timer@...600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0x3fe600 0x20>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_HIGH)>; > + clocks = <&clk NPCM7XX_CLK_AHB>; > + }; > + }; > +}; > -- > 2.22.0 >
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