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Message-ID: <CAMhs-H8axFToyEYUwtc1ZGMd9mOb3ixnha_trJ7C5yFz06xdbQ@mail.gmail.com>
Date:   Thu, 19 Nov 2020 10:35:38 +0100
From:   Sergio Paracuellos <sergio.paracuellos@...il.com>
To:     Chuanhong Guo <gch981213@...il.com>
Cc:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        John Crispin <john@...ozen.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Weijie Gao <hackpascal@...il.com>, jiaxun.yang@...goat.com,
        "open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>,
        "open list:MIPS" <linux-mips@...r.kernel.org>,
        "open list:STAGING SUBSYSTEM" <devel@...verdev.osuosl.org>,
        NeilBrown <neil@...wn.name>
Subject: Re: [PATCH v3 3/5] clk: ralink: add clock driver for mt7621 SoC

Hi,

On Thu, Nov 19, 2020 at 10:32 AM Chuanhong Guo <gch981213@...il.com> wrote:
>
> Hi!
>
> On Fri, Nov 13, 2020 at 11:46 PM Sergio Paracuellos
> <sergio.paracuellos@...il.com> wrote:
> > [...]
> > diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> > new file mode 100644
> > index 000000000000..cf6f9216379d
> > --- /dev/null
> > +++ b/drivers/clk/ralink/Makefile
>
> Why ralink? The clock design of mt7621 doesn't seem
> to be part of ralink legacy stuff, and ralink is already
> acquired by mediatek anyway.
> I think it should be put in drivers/clk/mediatek instead.

I don't really know. It seems in that directory only arm arch related
code from mediatek is included... but let's see what other people
think about this.

>
> --
> Regards,
> Chuanhong Guo

Best regards,
    Sergio Paracuellos

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