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Message-ID: <1605791419.19819.4.camel@mtksdaap41>
Date: Thu, 19 Nov 2020 21:10:19 +0800
From: Weiyi Lu <weiyi.lu@...iatek.com>
To: Enric Balletbo Serra <eballetbo@...il.com>
CC: Matthias Brugger <matthias.bgg@...il.com>,
Nicolas Boichat <drinkcat@...omium.org>,
Rob Herring <robh@...nel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
srv_heupstream <srv_heupstream@...iatek.com>
Subject: Re: [PATCH v3] arm64: dts: mediatek: Add mt8192 power domains
controller
On Thu, 2020-11-19 at 13:13 +0100, Enric Balletbo Serra wrote:
> Hi Weiyi,
>
> Thank you for the patch
>
> Missatge de Weiyi Lu <weiyi.lu@...iatek.com> del dia dj., 19 de nov.
> 2020 a les 11:48:
> >
> > Add power domains controller node for SoC mt8192
> >
> > Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
> > ---
> >
> > Change in v3: None, just rebase dts onto v5.10-rc1 and
> > V4 of series "Add new driver for SCPSYS power domains controller"[1]
> >
> > [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
> >
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++++++++++
> > 1 file changed, 201 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 69d45c7..08449eb 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -9,6 +9,7 @@
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interrupt-controller/irq.h>
> > #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> > +#include <dt-bindings/power/mt8192-power.h>
> >
> > / {
> > compatible = "mediatek,mt8192";
> > @@ -257,6 +258,206 @@
> > #interrupt-cells = <2>;
> > };
> >
> > + scpsys: syscon@...06000 {
> > + compatible = "syscon", "simple-mfd";
> > + reg = <0 0x10006000 0 0x1000>;
> > + #power-domain-cells = <1>;
> > +
> > + /* System Power Manager */
> > + spm: power-controller {
> > + compatible = "mediatek,mt8192-power-controller";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #power-domain-cells = <1>;
> > +
> > + /* power domain of the SoC */
> > + audio@...192_POWER_DOMAIN_AUDIO {
>
> If you run the dt_bindings_check it should return some errors, as all
> these node names should be 'power-domain@'. Which is a bit annoying
> because then you will get a bunch of errors like this:
>
> [ 1.969110] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 1.976997] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 1.984828] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 1.992657] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.000685] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.008566] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.016395] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.024221] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.032049] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.039874] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.047699] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.055524] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.063352] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
> [ 2.071176] debugfs: Directory 'power-domain' with parent
> 'pm_genpd' already present!
>
> But that's another problem that should be handled in debugfs system.
>
Indeed...so I chose to use different name in dts to avoid problems in
debugfs. It does violate the naming rules.
> > + reg = <MT8192_POWER_DOMAIN_AUDIO>;
> > + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> > + <&infracfg CLK_INFRA_AUDIO_26M_B>,
> > + <&infracfg CLK_INFRA_AUDIO>;
> > + clock-names = "audio", "audio1", "audio2";
> > + mediatek,infracfg = <&infracfg>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + conn@...192_POWER_DOMAIN_CONN {
> > + reg = <MT8192_POWER_DOMAIN_CONN>;
> > + clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
> > + clock-names = "conn";
> > + mediatek,infracfg = <&infracfg>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + mfg@...192_POWER_DOMAIN_MFG0 {
> > + reg = <MT8192_POWER_DOMAIN_MFG0>;
> > + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
> > + clock-names = "mfg";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #power-domain-cells = <1>;
> > +
> > + mfg1@...192_POWER_DOMAIN_MFG1 {
> > + reg = <MT8192_POWER_DOMAIN_MFG1>;
> > + mediatek,infracfg = <&infracfg>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #power-domain-cells = <1>;
> > +
> > + mfg2@...192_POWER_DOMAIN_MFG2 {
> > + reg = <MT8192_POWER_DOMAIN_MFG2>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + mfg3@...192_POWER_DOMAIN_MFG3 {
> > + reg = <MT8192_POWER_DOMAIN_MFG3>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + mfg4@...192_POWER_DOMAIN_MFG4 {
> > + reg = <MT8192_POWER_DOMAIN_MFG4>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + mfg5@...192_POWER_DOMAIN_MFG5 {
> > + reg = <MT8192_POWER_DOMAIN_MFG5>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + mfg6@...192_POWER_DOMAIN_MFG6 {
> > + reg = <MT8192_POWER_DOMAIN_MFG6>;
> > + #power-domain-cells = <0>;
> > + };
> > + };
> > + };
> > +
> > + disp@...192_POWER_DOMAIN_DISP {
> > + reg = <MT8192_POWER_DOMAIN_DISP>;
> > + clocks = <&topckgen CLK_TOP_DISP_SEL>,
> > + <&mmsys CLK_MM_SMI_INFRA>,
> > + <&mmsys CLK_MM_SMI_COMMON>,
> > + <&mmsys CLK_MM_SMI_GALS>,
> > + <&mmsys CLK_MM_SMI_IOMMU>;
> > + clock-names = "disp", "disp-0", "disp-1", "disp-2",
> > + "disp-3";
> > + mediatek,infracfg = <&infracfg>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #power-domain-cells = <1>;
> > +
> > + ipe@...192_POWER_DOMAIN_IPE {
> > + reg = <MT8192_POWER_DOMAIN_IPE>;
> > + clocks = <&topckgen CLK_TOP_IPE_SEL>,
> > + <&ipesys CLK_IPE_LARB19>,
> > + <&ipesys CLK_IPE_LARB20>,
> > + <&ipesys CLK_IPE_SMI_SUBCOM>,
> > + <&ipesys CLK_IPE_GALS>;
> > + clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
> > + "ipe-3";
> > + mediatek,infracfg = <&infracfg>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + isp@...192_POWER_DOMAIN_ISP {
> > + reg = <MT8192_POWER_DOMAIN_ISP>;
> > + clocks = <&topckgen CLK_TOP_IMG1_SEL>,
> > + <&imgsys CLK_IMG_LARB9>,
> > + <&imgsys CLK_IMG_GALS>;
> > + clock-names = "isp", "isp-0", "isp-1";
> > + mediatek,infracfg = <&infracfg>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + isp2@...192_POWER_DOMAIN_ISP2 {
> > + reg = <MT8192_POWER_DOMAIN_ISP2>;
> > + clocks = <&topckgen CLK_TOP_IMG2_SEL>,
> > + <&imgsys2 CLK_IMG2_LARB11>,
> > + <&imgsys2 CLK_IMG2_GALS>;
> > + clock-names = "isp2", "isp2-0", "isp2-1";
> > + mediatek,infracfg = <&infracfg>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + mdp@...192_POWER_DOMAIN_MDP {
> > + reg = <MT8192_POWER_DOMAIN_MDP>;
> > + clocks = <&topckgen CLK_TOP_MDP_SEL>,
> > + <&mdpsys CLK_MDP_SMI0>;
> > + clock-names = "mdp", "mdp-0";
> > + mediatek,infracfg = <&infracfg>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + venc@...192_POWER_DOMAIN_VENC {
> > + reg = <MT8192_POWER_DOMAIN_VENC>;
> > + clocks = <&topckgen CLK_TOP_VENC_SEL>,
> > + <&vencsys CLK_VENC_SET1_VENC>;
> > + clock-names = "venc", "venc-0";
> > + mediatek,infracfg = <&infracfg>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + vdec@...192_POWER_DOMAIN_VDEC {
> > + reg = <MT8192_POWER_DOMAIN_VDEC>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
> > + clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
> > + mediatek,infracfg = <&infracfg>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #power-domain-cells = <1>;
> > +
> > + vdec2@...192_POWER_DOMAIN_VDEC2 {
> > + reg = <MT8192_POWER_DOMAIN_VDEC2>;
> > + clocks = <&vdecsys CLK_VDEC_VDEC>,
> > + <&vdecsys CLK_VDEC_LAT>,
> > + <&vdecsys CLK_VDEC_LARB1>;
> > + clock-names = "vdec2-0", "vdec2-1",
> > + "vdec2-2";
> > + #power-domain-cells = <0>;
> > + };
> > + };
> > +
> > + cam@...192_POWER_DOMAIN_CAM {
> > + reg = <MT8192_POWER_DOMAIN_CAM>;
> > + clocks = <&topckgen CLK_TOP_CAM_SEL>,
> > + <&camsys CLK_CAM_LARB13>,
> > + <&camsys CLK_CAM_LARB14>,
> > + <&camsys CLK_CAM_CCU_GALS>,
> > + <&camsys CLK_CAM_CAM2MM_GALS>;
> > + clock-names = "cam", "cam-0", "cam-1", "cam-2",
> > + "cam-3";
> > + mediatek,infracfg = <&infracfg>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #power-domain-cells = <1>;
> > +
> > + cam_rawa@...192_POWER_DOMAIN_CAM_RAWA {
> > + reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
> > + clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
> > + clock-names = "cam_rawa-0";
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + cam_rawb@...192_POWER_DOMAIN_CAM_RAWB {
> > + reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
> > + clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
> > + clock-names = "cam_rawb-0";
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + cam_rawc@...192_POWER_DOMAIN_CAM_RAWC {
> > + reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
> > + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
> > + clock-names = "cam_rawc-0";
> > + #power-domain-cells = <0>;
> > + };
> > + };
> > + };
> > + };
> > + };
> > +
> > apmixedsys: syscon@...0c000 {
> > compatible = "mediatek,mt8192-apmixedsys", "syscon";
> > reg = <0 0x1000c000 0 0x1000>;
> > --
> > 1.8.1.1.dirty
> >
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